Commit 0b2ecf45 authored by Shawn Guo's avatar Shawn Guo
Browse files

Merge tag 'imx-soc-3.17' into imx/dt 

The i.MX SoC changes for 3.17:
 - Add devicetree support for i.MX1 and i.MX21 clock driver
 - Use CLOCKSOURCE_OF_DECLARE() to initialize timer for DT targets
 - Use of_clk_init() to initialize i.MX25 and i.MX27 clock driver in
   device tree boot
 - Remove i.MX1 camera support
 - Remove i.MX27 IP Camera and Lite-Kit board support
 - Add suspend and cpuidle support for i.mx6sx
 - Clean up unused clk_register_clkdev() lookups
 - Update imx-weim bus driver to support populating devices on a simple
   bus
 - Switch i.MX27 and i.MX6QDL clock driver to use macro for clock IDs
 - Make i.MX51 a DT only platform and clean up the non-DT support code
 - Support disabling supervisor protect via DT
 - Random defconfig updates
parents 4c834452 4349c429

Documentation/devicetree/bindings/clock/imx1-clock.txt

0 → 100644
+26 −0
Original line number Diff line number Diff line 
* Clock bindings for Freescale i.MX1 CPUs



Required properties:

- compatible: Should be "fsl,imx1-ccm".

- reg: Address and length of the register set.

- #clock-cells: Should be <1>.



The clock consumer should specify the desired clock by having the clock

ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx1-clock.h

for the full list of i.MX1 clock IDs.



Examples:

	clks: ccm@0021b000 {

		#clock-cells = <1>;

		compatible = "fsl,imx1-ccm";

		reg = <0x0021b000 0x1000>;

	};



	pwm: pwm@00208000 {

		#pwm-cells = <2>;

		compatible = "fsl,imx1-pwm";

		reg = <0x00208000 0x1000>;

		interrupts = <34>;

		clocks = <&clks IMX1_CLK_DUMMY>, <&clks IMX1_CLK_PER1>;

		clock-names = "ipg", "per";

	};

Documentation/devicetree/bindings/clock/imx21-clock.txt

0 → 100644
+28 −0
Original line number Diff line number Diff line 
* Clock bindings for Freescale i.MX21



Required properties:

- compatible  : Should be "fsl,imx21-ccm".

- reg         : Address and length of the register set.

- interrupts  : Should contain CCM interrupt.

- #clock-cells: Should be <1>.



The clock consumer should specify the desired clock by having the clock

ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx21-clock.h

for the full list of i.MX21 clock IDs.



Examples:

	clks: ccm@10027000{

		compatible = "fsl,imx21-ccm";

		reg = <0x10027000 0x800>;

		#clock-cells = <1>;

	};



	uart1: serial@1000a000 {

		compatible = "fsl,imx21-uart";

		reg = <0x1000a000 0x1000>;

		interrupts = <20>;

		clocks = <&clks IMX21_CLK_UART1_IPG_GATE>,

			 <&clks IMX21_CLK_PER1>;

		clock-names = "ipg", "per";

		status = "disabled";

	};

Documentation/devicetree/bindings/clock/imx27-clock.txt

+16 −111
Original line number Diff line number Diff line
@@ -7,106 +7,10 @@ Required properties: 
- #clock-cells: Should be <1>



The clock consumer should specify the desired clock by having the clock

ID in its "clocks" phandle cell.  The following is a full list of i.MX27

clocks and IDs.



	Clock		    ID

	-----------------------

	dummy                0

	ckih                 1

	ckil                 2

	mpll                 3

	spll                 4

	mpll_main2           5

	ahb                  6

	ipg                  7

	nfc_div              8

	per1_div             9

	per2_div             10

	per3_div             11

	per4_div             12

	vpu_sel              13

	vpu_div              14

	usb_div              15

	cpu_sel              16

	clko_sel             17

	cpu_div              18

	clko_div             19

	ssi1_sel             20

	ssi2_sel             21

	ssi1_div             22

	ssi2_div             23

	clko_en              24

	ssi2_ipg_gate        25

	ssi1_ipg_gate        26

	slcdc_ipg_gate       27

	sdhc3_ipg_gate       28

	sdhc2_ipg_gate       29

	sdhc1_ipg_gate       30

	scc_ipg_gate         31

	sahara_ipg_gate      32

	rtc_ipg_gate         33

	pwm_ipg_gate         34

	owire_ipg_gate       35

	lcdc_ipg_gate        36

	kpp_ipg_gate         37

	iim_ipg_gate         38

	i2c2_ipg_gate        39

	i2c1_ipg_gate        40

	gpt6_ipg_gate        41

	gpt5_ipg_gate        42

	gpt4_ipg_gate        43

	gpt3_ipg_gate        44

	gpt2_ipg_gate        45

	gpt1_ipg_gate        46

	gpio_ipg_gate        47

	fec_ipg_gate         48

	emma_ipg_gate        49

	dma_ipg_gate         50

	cspi3_ipg_gate       51

	cspi2_ipg_gate       52

	cspi1_ipg_gate       53

	nfc_baud_gate        54

	ssi2_baud_gate       55

	ssi1_baud_gate       56

	vpu_baud_gate        57

	per4_gate            58

	per3_gate            59

	per2_gate            60

	per1_gate            61

	usb_ahb_gate         62

	slcdc_ahb_gate       63

	sahara_ahb_gate      64

	lcdc_ahb_gate        65

	vpu_ahb_gate         66

	fec_ahb_gate         67

	emma_ahb_gate        68

	emi_ahb_gate         69

	dma_ahb_gate         70

	csi_ahb_gate         71

	brom_ahb_gate        72

	ata_ahb_gate         73

	wdog_ipg_gate        74

	usb_ipg_gate         75

	uart6_ipg_gate       76

	uart5_ipg_gate       77

	uart4_ipg_gate       78

	uart3_ipg_gate       79

	uart2_ipg_gate       80

	uart1_ipg_gate       81

	ckih_div1p5          82

	fpm                  83

	mpll_osc_sel         84

	mpll_sel             85

	spll_gate            86

	mshc_div             87

	rtic_ipg_gate        88

	mshc_ipg_gate        89

	rtic_ahb_gate        90

	mshc_baud_gate       91

ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx27-clock.h

for the full list of i.MX27 clock IDs.



Examples:



	clks: ccm@10027000{

		compatible = "fsl,imx27-ccm";

		reg = <0x10027000 0x1000>;
@@ -117,7 +21,8 @@ uart1: serial@1000a000 { 
		compatible = "fsl,imx27-uart", "fsl,imx21-uart";

		reg = <0x1000a000 0x1000>;

		interrupts = <20>;

	clocks = <&clks 81>, <&clks 61>;

		clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,

			 <&clks IMX27_CLK_PER1_GATE>;

		clock-names = "ipg", "per";

		status = "disabled";

	};

Documentation/devicetree/bindings/clock/imx6q-clock.txt

+5 −215
Original line number Diff line number Diff line
@@ -7,223 +7,13 @@ Required properties: 
- #clock-cells: Should be <1>



The clock consumer should specify the desired clock by having the clock

ID in its "clocks" phandle cell.  The following is a full list of i.MX6Q

clocks and IDs.



	Clock			ID

	---------------------------

	dummy			0

	ckil			1

	ckih			2

	osc			3

	pll2_pfd0_352m		4

	pll2_pfd1_594m		5

	pll2_pfd2_396m		6

	pll3_pfd0_720m		7

	pll3_pfd1_540m		8

	pll3_pfd2_508m		9

	pll3_pfd3_454m		10

	pll2_198m		11

	pll3_120m		12

	pll3_80m		13

	pll3_60m		14

	twd			15

	step			16

	pll1_sw			17

	periph_pre		18

	periph2_pre		19

	periph_clk2_sel		20

	periph2_clk2_sel	21

	axi_sel			22

	esai_sel		23

	asrc_sel		24

	spdif_sel		25

	gpu2d_axi		26

	gpu3d_axi		27

	gpu2d_core_sel		28

	gpu3d_core_sel		29

	gpu3d_shader_sel	30

	ipu1_sel		31

	ipu2_sel		32

	ldb_di0_sel		33

	ldb_di1_sel		34

	ipu1_di0_pre_sel	35

	ipu1_di1_pre_sel	36

	ipu2_di0_pre_sel	37

	ipu2_di1_pre_sel	38

	ipu1_di0_sel		39

	ipu1_di1_sel		40

	ipu2_di0_sel		41

	ipu2_di1_sel		42

	hsi_tx_sel		43

	pcie_axi_sel		44

	ssi1_sel		45

	ssi2_sel		46

	ssi3_sel		47

	usdhc1_sel		48

	usdhc2_sel		49

	usdhc3_sel		50

	usdhc4_sel		51

	enfc_sel		52

	emi_sel			53

	emi_slow_sel		54

	vdo_axi_sel		55

	vpu_axi_sel		56

	cko1_sel		57

	periph			58

	periph2			59

	periph_clk2		60

	periph2_clk2		61

	ipg			62

	ipg_per			63

	esai_pred		64

	esai_podf		65

	asrc_pred		66

	asrc_podf		67

	spdif_pred		68

	spdif_podf		69

	can_root		70

	ecspi_root		71

	gpu2d_core_podf		72

	gpu3d_core_podf		73

	gpu3d_shader		74

	ipu1_podf		75

	ipu2_podf		76

	ldb_di0_podf		77

	ldb_di1_podf		78

	ipu1_di0_pre		79

	ipu1_di1_pre		80

	ipu2_di0_pre		81

	ipu2_di1_pre		82

	hsi_tx_podf		83

	ssi1_pred		84

	ssi1_podf		85

	ssi2_pred		86

	ssi2_podf		87

	ssi3_pred		88

	ssi3_podf		89

	uart_serial_podf	90

	usdhc1_podf		91

	usdhc2_podf		92

	usdhc3_podf		93

	usdhc4_podf		94

	enfc_pred		95

	enfc_podf		96

	emi_podf		97

	emi_slow_podf		98

	vpu_axi_podf		99

	cko1_podf		100

	axi			101

	mmdc_ch0_axi_podf	102

	mmdc_ch1_axi_podf	103

	arm			104

	ahb			105

	apbh_dma		106

	asrc			107

	can1_ipg		108

	can1_serial		109

	can2_ipg		110

	can2_serial		111

	ecspi1			112

	ecspi2			113

	ecspi3			114

	ecspi4			115

	ecspi5			116

	enet			117

	esai			118

	gpt_ipg			119

	gpt_ipg_per		120

	gpu2d_core		121

	gpu3d_core		122

	hdmi_iahb		123

	hdmi_isfr		124

	i2c1			125

	i2c2			126

	i2c3			127

	iim			128

	enfc			129

	ipu1			130

	ipu1_di0		131

	ipu1_di1		132

	ipu2			133

	ipu2_di0		134

	ldb_di0			135

	ldb_di1			136

	ipu2_di1		137

	hsi_tx			138

	mlb			139

	mmdc_ch0_axi		140

	mmdc_ch1_axi		141

	ocram			142

	openvg_axi		143

	pcie_axi		144

	pwm1			145

	pwm2			146

	pwm3			147

	pwm4			148

	per1_bch		149

	gpmi_bch_apb		150

	gpmi_bch		151

	gpmi_io			152

	gpmi_apb		153

	sata			154

	sdma			155

	spba			156

	ssi1			157

	ssi2			158

	ssi3			159

	uart_ipg		160

	uart_serial		161

	usboh3			162

	usdhc1			163

	usdhc2			164

	usdhc3			165

	usdhc4			166

	vdo_axi			167

	vpu_axi			168

	cko1			169

	pll1_sys		170

	pll2_bus		171

	pll3_usb_otg		172

	pll4_audio		173

	pll5_video		174

	pll8_mlb		175

	pll7_usb_host		176

	pll6_enet		177

	ssi1_ipg		178

	ssi2_ipg		179

	ssi3_ipg		180

	rom			181

	usbphy1			182

	usbphy2			183

	ldb_di0_div_3_5		184

	ldb_di1_div_3_5		185

	sata_ref		186

	sata_ref_100m		187

	pcie_ref		188

	pcie_ref_125m		189

	enet_ref		190

	usbphy1_gate		191

	usbphy2_gate		192

	pll4_post_div		193

	pll5_post_div		194

	pll5_video_div		195

	eim_slow      		196

	spdif      		197

	cko2_sel      		198

	cko2_podf      		199

	cko2      		200

	cko      		201

	vdoa      		202

	pll4_audio_div		203

	lvds1_sel		204

	lvds2_sel		205

	lvds1_gate		206

	lvds2_gate		207

	esai_ahb		208

ID in its "clocks" phandle cell.  See include/dt-bindings/clock/imx6qdl-clock.h

for the full list of i.MX6 Quad and DualLite clock IDs.



Examples:



#include <dt-bindings/clock/imx6qdl-clock.h>



clks: ccm@020c4000 {

	compatible = "fsl,imx6q-ccm";

	reg = <0x020c4000 0x4000>;
@@ -235,7 +25,7 @@ uart1: serial@02020000 { 
	compatible = "fsl,imx6q-uart", "fsl,imx21-uart";

	reg = <0x02020000 0x4000>;

	interrupts = <0 26 0x04>;

	clocks = <&clks 160>, <&clks 161>;

	clocks = <&clks IMX6QDL_CLK_UART_IPG>, <&clks IMX6QDL_CLK_UART_SERIAL>;

	clock-names = "ipg", "per";

	status = "disabled";

};

arch/arm/configs/imx_v4_v5_defconfig

+3 −2
Original line number Diff line number Diff line 
# CONFIG_SWAP is not set

CONFIG_SYSVIPC=y

CONFIG_POSIX_MQUEUE=y

CONFIG_FHANDLE=y

CONFIG_NO_HZ=y

CONFIG_HIGH_RES_TIMERS=y

CONFIG_LOG_BUF_SHIFT=14
@@ -35,10 +36,8 @@ CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2=y 
CONFIG_MACH_EUKREA_CPUIMX27_USEUART4=y

CONFIG_MACH_MX27_3DS=y

CONFIG_MACH_IMX27_VISSTRIM_M10=y

CONFIG_MACH_IMX27LITE=y

CONFIG_MACH_PCA100=y

CONFIG_MACH_MXT_TD60=y

CONFIG_MACH_IMX27IPCAM=y

CONFIG_MACH_IMX27_DT=y

CONFIG_PREEMPT=y

CONFIG_AEABI=y
@@ -159,6 +158,8 @@ CONFIG_USB_CHIPIDEA=y 
CONFIG_USB_CHIPIDEA_UDC=y

CONFIG_USB_CHIPIDEA_HOST=y

CONFIG_NOP_USB_XCEIV=y

CONFIG_USB_GADGET=y

CONFIG_USB_ETH=m

CONFIG_MMC=y

CONFIG_MMC_SDHCI=y

CONFIG_MMC_SDHCI_PLTFM=y

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