Commit 0b2a8e09 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: Improve gen3/4 frame counter 



Currently the logic to fix up the frame counter on gen3/4 assumes that
start of vblank occurs at vblank_start*htotal pixels, when in fact
it occurs htotal-hsync_start pixels earlier. Apply the appropriate
adjustment to make the frame counter more accurate.

Also fix the vblank start position for interlaced display modes.

Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatar"Akash Goel <akash.goels@gmail.com&gt;">
Reviewed-by: default avatar"Sourab Gupta <sourabgupta@gmail.com&gt;">
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 7e78f1cb

drivers/gpu/drm/i915/i915_irq.c

+16 −5
Original line number Diff line number Diff line
@@ -754,7 +754,7 @@ static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) 
	struct drm_i915_private *dev_priv = dev->dev_private;

	unsigned long high_frame;

	unsigned long low_frame;

	u32 high1, high2, low, pixel, vbl_start;

	u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;



	if (!i915_pipe_enabled(dev, pipe)) {

		DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
@@ -768,16 +768,27 @@ static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) 
		const struct drm_display_mode *mode =

			&intel_crtc->config.adjusted_mode;



		vbl_start = mode->crtc_vblank_start * mode->crtc_htotal;

		htotal = mode->crtc_htotal;

		hsync_start = mode->crtc_hsync_start;

		vbl_start = mode->crtc_vblank_start;

		if (mode->flags & DRM_MODE_FLAG_INTERLACE)

			vbl_start = DIV_ROUND_UP(vbl_start, 2);

	} else {

		enum transcoder cpu_transcoder = (enum transcoder) pipe;

		u32 htotal;



		htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;

		hsync_start = (I915_READ(HSYNC(cpu_transcoder))  & 0x1fff) + 1;

		vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;

		if ((I915_READ(PIPECONF(cpu_transcoder)) &

		     PIPECONF_INTERLACE_MASK) != PIPECONF_PROGRESSIVE)

			vbl_start = DIV_ROUND_UP(vbl_start, 2);

	}



	/* Convert to pixel count */

	vbl_start *= htotal;

	}



	/* Start of vblank event occurs at start of hsync */

	vbl_start -= htotal - hsync_start;



	high_frame = PIPEFRAME(pipe);

	low_frame = PIPEFRAMEPIXEL(pipe);

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