Commit 0b0ee66c authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/ioremap' into next 

* pci/ioremap:
  PCI: versatile: Update PCI config space remap function
  PCI: keystone-dw: Update PCI config space remap function
  PCI: layerscape: Update PCI config space remap function
  PCI: hisi: Update PCI config space remap function
  PCI: tegra: Update PCI config space remap function
  PCI: xgene: Update PCI config space remap function
  PCI: armada8k: Update PCI config space remap function
  PCI: designware: Update PCI config space remap function
  PCI: iproc-platform: Update PCI config space remap function
  PCI: qcom: Update PCI config space remap function
  PCI: rockchip: Update PCI config space remap function
  PCI: spear13xx: Update PCI config space remap function
  PCI: xilinx-nwl: Update PCI config space remap function
  PCI: xilinx: Update PCI config space remap function
  PCI: ECAM: Map config region with pci_remap_cfgspace()
  PCI: Implement devm_pci_remap_cfgspace()
  devres: fix devm_ioremap_*() offset parameter kerneldoc description
  ARM: Implement pci_remap_cfgspace() interface
  ARM64: Implement pci_remap_cfgspace() interface
  linux/io.h: Add pci_remap_cfgspace() interface
  PCI: Remove __weak tag from pci_remap_iospace()
parents 27e99676 bc636ee9

Documentation/driver-model/devres.txt

+4 −2
Original line number Diff line number Diff line
@@ -342,6 +342,8 @@ PER-CPU MEM 
  devm_free_percpu()



PCI

  devm_pci_remap_cfgspace()	: ioremap PCI configuration space

  devm_pci_remap_cfg_resource()	: ioremap PCI configuration space resource

  pcim_enable_device()		: after success, all PCI ops become managed

  pcim_pin_device()		: keep PCI device enabled after release

arch/arm/include/asm/io.h

+10 −0
Original line number Diff line number Diff line
@@ -186,6 +186,16 @@ static inline void pci_ioremap_set_mem_type(int mem_type) {} 


extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr);



/*

 * PCI configuration space mapping function.

 *

 * The PCI specification does not allow configuration write

 * transactions to be posted. Add an arch specific

 * pci_remap_cfgspace() definition that is implemented

 * through strongly ordered memory mappings.

 */

#define pci_remap_cfgspace pci_remap_cfgspace

void __iomem *pci_remap_cfgspace(resource_size_t res_cookie, size_t size);

/*

 * Now, pick up the machine-defined IO definitions

 */

arch/arm/mm/ioremap.c

+7 −0
Original line number Diff line number Diff line
@@ -481,6 +481,13 @@ int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr) 
				  __pgprot(get_mem_type(pci_ioremap_mem_type)->prot_pte));

}

EXPORT_SYMBOL_GPL(pci_ioremap_io);



void __iomem *pci_remap_cfgspace(resource_size_t res_cookie, size_t size)

{

	return arch_ioremap_caller(res_cookie, size, MT_UNCACHED,

				   __builtin_return_address(0));

}

EXPORT_SYMBOL_GPL(pci_remap_cfgspace);

#endif



/*

arch/arm/mm/nommu.c

+12 −0
Original line number Diff line number Diff line
@@ -433,6 +433,18 @@ void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size) 
}

EXPORT_SYMBOL(ioremap_wc);



#ifdef CONFIG_PCI



#include <asm/mach/map.h>



void __iomem *pci_remap_cfgspace(resource_size_t res_cookie, size_t size)

{

	return arch_ioremap_caller(res_cookie, size, MT_UNCACHED,

				   __builtin_return_address(0));

}

EXPORT_SYMBOL_GPL(pci_remap_cfgspace);

#endif



void *arch_memremap_wb(phys_addr_t phys_addr, size_t size)

{

	return (void *)phys_addr;

arch/arm64/include/asm/io.h

+10 −0
Original line number Diff line number Diff line
@@ -172,6 +172,16 @@ extern void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size); 
#define ioremap_wt(addr, size)		__ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))

#define iounmap				__iounmap



/*

 * PCI configuration space mapping function.

 *

 * The PCI specification disallows posted write configuration transactions.

 * Add an arch specific pci_remap_cfgspace() definition that is implemented

 * through nGnRnE device memory attribute as recommended by the ARM v8

 * Architecture reference manual Issue A.k B2.8.2 "Device memory".

 */

#define pci_remap_cfgspace(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRnE))



/*

 * io{read,write}{16,32,64}be() macros

 */

CRA Git | Maintained and supported by SUSTech CRA and CCSE