Commit 0b076ecd authored by Daniel Vetter's avatar Daniel Vetter
Browse files

Merge remote-tracking branch 'airlied/drm-next' into HEAD 



Backmerge drm-next because the conflict between Ander's atomic fixes
for 4.2 and Maartens future work are getting to unwielding to handle.

Conflicts:
	drivers/gpu/drm/i915/intel_display.c
	drivers/gpu/drm/i915/intel_ringbuffer.h

Just always take ours, same as git merge -X ours, but done by hand
because I didn't trust git: It's confusing that it doesn't show any
conflicts in the merge diff at all.

Signed-off-by: default avatarDaniel Vetter <daniel.vetter@intel.com>
parents c82435bb 9eb1e57f

Documentation/DocBook/drm.tmpl

+18 −23
Original line number Diff line number Diff line
@@ -2585,7 +2585,22 @@ void intel_crt_init(struct drm_device *dev) 
	<td valign="top" >Description/Restrictions</td>

	</tr>

	<tr>

	<td rowspan="36" valign="top" >DRM</td>

	<td rowspan="37" valign="top" >DRM</td>

	<td valign="top" >Generic</td>

	<td valign="top" >“rotation”</td>

	<td valign="top" >BITMASK</td>

	<td valign="top" >{ 0, "rotate-0" },

	{ 1, "rotate-90" },

	{ 2, "rotate-180" },

	{ 3, "rotate-270" },

	{ 4, "reflect-x" },

	{ 5, "reflect-y" }</td>

	<td valign="top" >CRTC, Plane</td>

	<td valign="top" >rotate-(degrees) rotates the image by the specified amount in degrees

	in counter clockwise direction. reflect-x and reflect-y reflects the

	image along the specified axis prior to rotation</td>

	</tr>

	<tr>

	<td rowspan="5" valign="top" >Connector</td>

	<td valign="top" >“EDID”</td>

	<td valign="top" >BLOB | IMMUTABLE</td>
@@ -2846,7 +2861,7 @@ void intel_crt_init(struct drm_device *dev) 
	<td valign="top" >TBD</td>

	</tr>

	<tr>

	<td rowspan="21" valign="top" >i915</td>

	<td rowspan="20" valign="top" >i915</td>

	<td rowspan="2" valign="top" >Generic</td>

	<td valign="top" >"Broadcast RGB"</td>

	<td valign="top" >ENUM</td>
@@ -2862,14 +2877,6 @@ void intel_crt_init(struct drm_device *dev) 
	<td valign="top" >TBD</td>

	</tr>

	<tr>

	<td rowspan="1" valign="top" >Plane</td>

	<td valign="top" >“rotation”</td>

	<td valign="top" >BITMASK</td>

	<td valign="top" >{ 0, "rotate-0" }, { 2, "rotate-180" }</td>

	<td valign="top" >Plane</td>

	<td valign="top" >TBD</td>

	</tr>

	<tr>

	<td rowspan="17" valign="top" >SDVO-TV</td>

	<td valign="top" >“mode”</td>

	<td valign="top" >ENUM</td>
@@ -3377,19 +3384,7 @@ void intel_crt_init(struct drm_device *dev) 
	</tr>

	<tr>

	<td rowspan="2" valign="top" >omap</td>

	<td rowspan="2" valign="top" >Generic</td>

	<td valign="top" >“rotation”</td>

	<td valign="top" >BITMASK</td>

	<td valign="top" >{ 0, "rotate-0" },

	{ 1, "rotate-90" },

	{ 2, "rotate-180" },

	{ 3, "rotate-270" },

	{ 4, "reflect-x" },

	{ 5, "reflect-y" }</td>

	<td valign="top" >CRTC, Plane</td>

	<td valign="top" >TBD</td>

	</tr>

	<tr>

	<td valign="top" >Generic</td>

	<td valign="top" >“zorder”</td>

	<td valign="top" >RANGE</td>

	<td valign="top" >Min=0, Max=3</td>

Documentation/devicetree/bindings/drm/msm/dsi.txt

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+120 −0
Original line number Diff line number Diff line 
Qualcomm Technologies Inc. adreno/snapdragon DSI output



DSI Controller:

Required properties:

- compatible:

  * "qcom,mdss-dsi-ctrl"

- reg: Physical base address and length of the registers of controller

- reg-names: The names of register regions. The following regions are required:

  * "dsi_ctrl"

- qcom,dsi-host-index: The ID of DSI controller hardware instance. This should

  be 0 or 1, since we have 2 DSI controllers at most for now.

- interrupts: The interrupt signal from the DSI block.

- power-domains: Should be <&mmcc MDSS_GDSC>.

- clocks: device clocks

  See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.

- clock-names: the following clocks are required:

  * "bus_clk"

  * "byte_clk"

  * "core_clk"

  * "core_mmss_clk"

  * "iface_clk"

  * "mdp_core_clk"

  * "pixel_clk"

- vdd-supply: phandle to vdd regulator device node

- vddio-supply: phandle to vdd-io regulator device node

- vdda-supply: phandle to vdda regulator device node

- qcom,dsi-phy: phandle to DSI PHY device node



Optional properties:

- panel@0: Node of panel connected to this DSI controller.

  See files in Documentation/devicetree/bindings/panel/ for each supported

  panel.

- qcom,dual-panel-mode: Boolean value indicating if the DSI controller is

  driving a panel which needs 2 DSI links.

- qcom,master-panel: Boolean value indicating if the DSI controller is driving

  the master link of the 2-DSI panel.

- qcom,sync-dual-panel: Boolean value indicating if the DSI controller is

  driving a 2-DSI panel whose 2 links need receive command simultaneously.

- interrupt-parent: phandle to the MDP block if the interrupt signal is routed

  through MDP block



DSI PHY:

Required properties:

- compatible: Could be the following

  * "qcom,dsi-phy-28nm-hpm"

  * "qcom,dsi-phy-28nm-lp"

- reg: Physical base address and length of the registers of PLL, PHY and PHY

  regulator

- reg-names: The names of register regions. The following regions are required:

  * "dsi_pll"

  * "dsi_phy"

  * "dsi_phy_regulator"

- qcom,dsi-phy-index: The ID of DSI PHY hardware instance. This should

  be 0 or 1, since we have 2 DSI PHYs at most for now.

- power-domains: Should be <&mmcc MDSS_GDSC>.

- clocks: device clocks

  See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.

- clock-names: the following clocks are required:

  * "iface_clk"

- vddio-supply: phandle to vdd-io regulator device node



Example:

	mdss_dsi0: qcom,mdss_dsi@fd922800 {

		compatible = "qcom,mdss-dsi-ctrl";

		qcom,dsi-host-index = <0>;

		interrupt-parent = <&mdss_mdp>;

		interrupts = <4 0>;

		reg-names = "dsi_ctrl";

		reg = <0xfd922800 0x200>;

		power-domains = <&mmcc MDSS_GDSC>;

		clock-names =

			"bus_clk",

			"byte_clk",

			"core_clk",

			"core_mmss_clk",

			"iface_clk",

			"mdp_core_clk",

			"pixel_clk";

		clocks =

			<&mmcc MDSS_AXI_CLK>,

			<&mmcc MDSS_BYTE0_CLK>,

			<&mmcc MDSS_ESC0_CLK>,

			<&mmcc MMSS_MISC_AHB_CLK>,

			<&mmcc MDSS_AHB_CLK>,

			<&mmcc MDSS_MDP_CLK>,

			<&mmcc MDSS_PCLK0_CLK>;

		vdda-supply = <&pma8084_l2>;

		vdd-supply = <&pma8084_l22>;

		vddio-supply = <&pma8084_l12>;



		qcom,dsi-phy = <&mdss_dsi_phy0>;



		qcom,dual-panel-mode;

		qcom,master-panel;

		qcom,sync-dual-panel;



		panel: panel@0 {

			compatible = "sharp,lq101r1sx01";

			reg = <0>;

			link2 = <&secondary>;



			power-supply = <...>;

			backlight = <...>;

		};

	};



	mdss_dsi_phy0: qcom,mdss_dsi_phy@fd922a00 {

		compatible = "qcom,dsi-phy-28nm-hpm";

		qcom,dsi-phy-index = <0>;

		reg-names =

			"dsi_pll",

			"dsi_phy",

			"dsi_phy_regulator";

		reg =   <0xfd922a00 0xd4>,

			<0xfd922b00 0x2b0>,

			<0xfd922d80 0x7b>;

		clock-names = "iface_clk";

		clocks = <&mmcc MDSS_AHB_CLK>;

		vddio-supply = <&pma8084_l12>;

	};

Documentation/devicetree/bindings/drm/msm/edp.txt

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+60 −0
Original line number Diff line number Diff line 
Qualcomm Technologies Inc. adreno/snapdragon eDP output



Required properties:

- compatible:

  * "qcom,mdss-edp"

- reg: Physical base address and length of the registers of controller and PLL

- reg-names: The names of register regions. The following regions are required:

  * "edp"

  * "pll_base"

- interrupts: The interrupt signal from the eDP block.

- power-domains: Should be <&mmcc MDSS_GDSC>.

- clocks: device clocks

  See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.

- clock-names: the following clocks are required:

  * "core_clk"

  * "iface_clk"

  * "mdp_core_clk"

  * "pixel_clk"

  * "link_clk"

- #clock-cells: The value should be 1.

- vdda-supply: phandle to vdda regulator device node

- lvl-vdd-supply: phandle to regulator device node which is used to supply power

  to HPD receiving chip

- panel-en-gpios: GPIO pin to supply power to panel.

- panel-hpd-gpios: GPIO pin used for eDP hpd.





Optional properties:

- interrupt-parent: phandle to the MDP block if the interrupt signal is routed

  through MDP block



Example:

	mdss_edp: qcom,mdss_edp@fd923400 {

			compatible = "qcom,mdss-edp";

			reg-names =

				"edp",

				"pll_base";

			reg =	<0xfd923400 0x700>,

				<0xfd923a00 0xd4>;

			interrupt-parent = <&mdss_mdp>;

			interrupts = <12 0>;

			power-domains = <&mmcc MDSS_GDSC>;

			clock-names =

				"core_clk",

				"pixel_clk",

				"iface_clk",

				"link_clk",

				"mdp_core_clk";

			clocks =

				<&mmcc MDSS_EDPAUX_CLK>,

				<&mmcc MDSS_EDPPIXEL_CLK>,

				<&mmcc MDSS_AHB_CLK>,

				<&mmcc MDSS_EDPLINK_CLK>,

				<&mmcc MDSS_MDP_CLK>;

			#clock-cells = <1>;

			vdda-supply = <&pma8084_l12>;

			lvl-vdd-supply = <&lvl_vreg>;

			panel-en-gpios = <&tlmm 137 0>;

			panel-hpd-gpios = <&tlmm 103 0>;

	};

Documentation/devicetree/bindings/drm/msm/hdmi.txt

+6 −0
Original line number Diff line number Diff line
@@ -20,6 +20,9 @@ Required properties: 
Optional properties:

- qcom,hdmi-tx-mux-en-gpio: hdmi mux enable pin

- qcom,hdmi-tx-mux-sel-gpio: hdmi mux select pin

- pinctrl-names: the pin control state names; should contain "default"

- pinctrl-0: the default pinctrl state (active)

- pinctrl-1: the "sleep" pinctrl state



Example:
@@ -44,5 +47,8 @@ Example: 
		qcom,hdmi-tx-hpd = <&msmgpio 72 GPIO_ACTIVE_HIGH>;

		core-vdda-supply = <&pm8921_hdmi_mvs>;

		hdmi-mux-supply = <&ext_3p3v>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&hpd_active  &ddc_active  &cec_active>;

		pinctrl-1 = <&hpd_suspend &ddc_suspend &cec_suspend>;

	};

};

Documentation/devicetree/bindings/panel/hannstar,hsd100pxn1.txt

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+7 −0
Original line number Diff line number Diff line 
HannStar Display Corp. HSD100PXN1 10.1" XGA LVDS panel



Required properties:

- compatible: should be "hannstar,hsd100pxn1"



This binding is compatible with the simple-panel binding, which is specified

in simple-panel.txt in this directory.

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