Commit 0aec75a5 authored Dec 08, 2020 by Heiner Kallweit Committed by Bjorn Helgaas Dec 08, 2020

PCI: Reduce pci_set_cacheline_size() message to debug level

Drivers like ehci_hcd and xhci_hcd use pci_set_mwi() and emit an annnoying
message like the following that results in user questions whether something
is broken:

  xhci_hcd 0000:00:15.0: cache line size of 64 is not supported

Root cause of the message is that on several chips the Cache Line Size
register is hard-wired to 0.

Change this message to debug level; an interested caller can still inform
the user (if deemed helpful) based on the return code.

Link: https://lore.kernel.org/r/be1ed3a2-98b9-ee1d-20b8-477f3d93961d@gmail.com


Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

parent b577562c

drivers/pci/pci.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -4317,7 +4317,7 @@ int pci_set_cacheline_size(struct pci_dev *dev)
		if (cacheline_size == pci_cache_line_size)
		return 0;

		pci_info(dev, "cache line size of %d is not supported\n",
		pci_dbg(dev, "cache line size of %d is not supported\n",
		pci_cache_line_size << 2);

		return -EINVAL;

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