Commit 0ab5171b authored Nov 30, 2016 by Balbir Singh Committed by Michael Ellerman Nov 30, 2016

powerpc/mm: Fix no execute fault handling on pre-POWER5



Aneesh/Ben reported that the change to do_page_fault() we made in commit
1d18ad02 ("powerpc/mm: Detect instruction fetch denied and report")
needs to handle the case where CPU_FTR_COHERENT_ICACHE is missing but we
have CPU_FTR_NOEXECUTE. In those cases the check added for
SRR1_ISI_N_OR_G might trigger a false positive.

This patch adds a check for CPU_FTR_COHERENT_ICACHE in addition to the
MSR value.

Fixes: 1d18ad02 ("powerpc/mm: Detect instruction fetch denied and report")
Reported-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Balbir Singh <bsingharora@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

parent f0f7fe1a

arch/powerpc/mm/fault.c

+9 −1

Original line number	Diff line number	Diff line
		@@ -392,8 +392,16 @@ good_area:
		if (is_exec) {
		/*
		* An execution fault + no execute ?
		*
		* On CPUs that don't have CPU_FTR_COHERENT_ICACHE we
		* deliberately create NX mappings, and use the fault to do the
		* cache flush. This is usually handled in hash_page_do_lazy_icache()
		* but we could end up here if that races with a concurrent PTE
		* update. In that case we need to fall through here to the VMA
		* check below.
		*/
		if (regs->msr & SRR1_ISI_N_OR_G)
		if (cpu_has_feature(CPU_FTR_COHERENT_ICACHE) &&
		(regs->msr & SRR1_ISI_N_OR_G))
		goto bad_area;

		/*

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