Commit 0aa821d8 authored Apr 20, 2018 by Stefan Agner Committed by Greg Kroah-Hartman Apr 23, 2018

serial: imx: fix cached UCR2 read on software reset



To reset the UART the SRST needs be cleared (low active). According
to the documentation the bit will remain active for 4 module clocks
until it is cleared (set to 1).

Hence the real register need to be read in case the cached register
indicates that the SRST bit is zero.

This bug lead to wrong baudrate because the baud rate register got
restored before reset completed in imx_flush_buffer.

Fixes: 3a0ab62f ("serial: imx: implement shadow registers for UCRx and UFCR")
Signed-off-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

parent 6d215f83

drivers/tty/serial/imx.c

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -316,7 +316,7 @@ static u32 imx_uart_readl(struct imx_port *sport, u32 offset)
	* differ from the value that was last written. As it only		* differ from the value that was last written. As it only
	* clears after being set, reread conditionally.		* clears after being set, reread conditionally.
	*/		*/
	if (sport->ucr2 & UCR2_SRST)		if (!(sport->ucr2 & UCR2_SRST))
	sport->ucr2 = readl(sport->port.membase + offset);		sport->ucr2 = readl(sport->port.membase + offset);
	return sport->ucr2;		return sport->ucr2;
	break;		break;

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