Commit 0aa0e0d6 authored Jan 28, 2020 by Kan Liang Committed by Ingo Molnar Feb 11, 2020

perf/x86/msr: Add Tremont support



Tremont is Intel's successor to Goldmont Plus. SMI_COUNT MSR is also
supported.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Link: https://lkml.kernel.org/r/1580236279-35492-3-git-send-email-kan.liang@linux.intel.com

parent ecf71fbc

arch/x86/events/msr.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -75,8 +75,9 @@ static bool test_intel(int idx, void *data)

		case INTEL_FAM6_ATOM_GOLDMONT:
		case INTEL_FAM6_ATOM_GOLDMONT_D:

		case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
		case INTEL_FAM6_ATOM_TREMONT_D:
		case INTEL_FAM6_ATOM_TREMONT:

		case INTEL_FAM6_XEON_PHI_KNL:
		case INTEL_FAM6_XEON_PHI_KNM:

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