ARC: perf: support cache hit/miss ratio (0a8a4767) · Commits · 戴 / test

arch/arc/include/asm/perf_event.h

+12 −5

Original line number	Diff line number	Diff line
		@@ -54,7 +54,10 @@ struct arc_reg_cc_build {
		#define PERF_COUNT_ARC_BPOK (PERF_COUNT_HW_MAX + 3)
		#define PERF_COUNT_ARC_EDTLB (PERF_COUNT_HW_MAX + 4)
		#define PERF_COUNT_ARC_EITLB (PERF_COUNT_HW_MAX + 5)
		#define PERF_COUNT_ARC_HW_MAX (PERF_COUNT_HW_MAX + 6)
		#define PERF_COUNT_ARC_LDC (PERF_COUNT_HW_MAX + 6)
		#define PERF_COUNT_ARC_STC (PERF_COUNT_HW_MAX + 7)

		#define PERF_COUNT_ARC_HW_MAX (PERF_COUNT_HW_MAX + 8)

		/*
		* Some ARC pct quirks:
		@@ -96,6 +99,9 @@ static const char * const arc_pmu_ev_hw_map[] = {
		[PERF_COUNT_ARC_BPOK] = "bpok", /* NP-NT, PT-T, PNT-NT */
		[PERF_COUNT_HW_BRANCH_MISSES] = "bpfail", /* NP-T, PT-NT, PNT-T */

		[PERF_COUNT_ARC_LDC] = "imemrdc", /* Instr: mem read cached */
		[PERF_COUNT_ARC_STC] = "imemwrc", /* Instr: mem write cached */

		[PERF_COUNT_ARC_DCLM] = "dclm", /* D-cache Load Miss */
		[PERF_COUNT_ARC_DCSM] = "dcsm", /* D-cache Store Miss */
		[PERF_COUNT_ARC_ICM] = "icm", /* I-cache Miss */
		@@ -109,11 +115,11 @@ static const char * const arc_pmu_ev_hw_map[] = {
		static const unsigned arc_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
		[C(L1D)] = {
		[C(OP_READ)] = {
		[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
		[C(RESULT_ACCESS)] = PERF_COUNT_ARC_LDC,
		[C(RESULT_MISS)] = PERF_COUNT_ARC_DCLM,
		},
		[C(OP_WRITE)] = {
		[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
		[C(RESULT_ACCESS)] = PERF_COUNT_ARC_STC,
		[C(RESULT_MISS)] = PERF_COUNT_ARC_DCSM,
		},
		[C(OP_PREFETCH)] = {
		@@ -123,7 +129,7 @@ static const unsigned arc_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
		},
		[C(L1I)] = {
		[C(OP_READ)] = {
		[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
		[C(RESULT_ACCESS)] = PERF_COUNT_HW_INSTRUCTIONS,
		[C(RESULT_MISS)] = PERF_COUNT_ARC_ICM,
		},
		[C(OP_WRITE)] = {
		@@ -151,9 +157,10 @@ static const unsigned arc_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
		},
		[C(DTLB)] = {
		[C(OP_READ)] = {
		[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
		[C(RESULT_ACCESS)] = PERF_COUNT_ARC_LDC,
		[C(RESULT_MISS)] = PERF_COUNT_ARC_EDTLB,
		},
		/* DTLB LD/ST Miss not segregated by h/w*/
		[C(OP_WRITE)] = {
		[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
		[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,

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