powerpc/lib/sstep: Fix fixed-point shift instructions that set CA32 (0a75aff1) · Commits · 戴 / test

This fixes the emulated behaviour of existing fixed-point shift right algebraic instructions that are supposed to set both the CA and CA32 bits of XER when running on a system that is compliant with POWER ISA v3.0 independent of whether the system is executing in 32-bit mode or 64-bit mode. The following instructions are affected: * Shift Right Algebraic Word Immediate (srawi[.]) * Shift Right Algebraic Word (sraw[.]) * Shift Right Algebraic Doubleword Immediate (sradi[.]) * Shift Right Algebraic Doubleword (srad[.]) Fixes: ("powerpc: Emulate most Book I instructions in emulate_step()") Signed-off-by:

Sandipan Das <sandipan@linux.vnet.ibm.com> Signed-off-by:

Michael Ellerman <mpe@ellerman.id.au>

arch/powerpc/lib/sstep.c

+4 −0

Original line number	Diff line number	Diff line
		@@ -1804,6 +1804,7 @@ int analyse_instr(struct instruction_op op, const struct pt_regs regs,
		op->xerval \|= XER_CA;
		else
		op->xerval &= ~XER_CA;
		set_ca32(op, op->xerval & XER_CA);
		goto logical_done;

		case 824: /* srawi */
		@@ -1816,6 +1817,7 @@ int analyse_instr(struct instruction_op op, const struct pt_regs regs,
		op->xerval \|= XER_CA;
		else
		op->xerval &= ~XER_CA;
		set_ca32(op, op->xerval & XER_CA);
		goto logical_done;

		#ifdef __powerpc64__
		@@ -1845,6 +1847,7 @@ int analyse_instr(struct instruction_op op, const struct pt_regs regs,
		op->xerval \|= XER_CA;
		else
		op->xerval &= ~XER_CA;
		set_ca32(op, op->xerval & XER_CA);
		goto logical_done;

		case 826: /* sradi with sh_5 = 0 */
		@@ -1858,6 +1861,7 @@ int analyse_instr(struct instruction_op op, const struct pt_regs regs,
		op->xerval \|= XER_CA;
		else
		op->xerval &= ~XER_CA;
		set_ca32(op, op->xerval & XER_CA);
		goto logical_done;
		#endif /* __powerpc64__ */

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