Commit 0a72ef89 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux 

Pull more arm64 fixes from Will Deacon:

 - Fix incorrect LDADD instruction encoding in our disassembly macros

 - Disable the broken ARM64_PSEUDO_NMI support for now

 - Add workaround for Cortex-A76 CPU erratum #1463225

 - Handle Cortex-A76/Neoverse-N1 erratum #1418040 w/ existing workaround

 - Fix IORT build failure if IOMMU_SUPPORT=n

 - Fix place-relative module relocation range checking and its
   interaction with KASLR

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64: insn: Add BUILD_BUG_ON() for invalid masks
  arm64: insn: Fix ldadd instruction encoding
  arm64: Kconfig: Make ARM64_PSEUDO_NMI depend on BROKEN for now
  arm64: Handle erratum 1418040 as a superset of erratum 1188873
  arm64/module: deal with ambiguity in PRELxx relocation ranges
  ACPI/IORT: Fix build error when IOMMU_SUPPORT is disabled
  arm64/kernel: kaslr: reduce module randomization range to 2 GB
  arm64: errata: Add workaround for Cortex-A76 erratum #1463225
  arm64: Remove useless message during oops
parents c50bbf61 edbcf50e

Documentation/arm64/silicon-errata.txt

+5 −4
Original line number Diff line number Diff line
@@ -58,13 +58,14 @@ stable kernels. 
| ARM            | Cortex-A72      | #853709         | N/A                         |

| ARM            | Cortex-A73      | #858921         | ARM64_ERRATUM_858921        |

| ARM            | Cortex-A55      | #1024718        | ARM64_ERRATUM_1024718       |

| ARM            | Cortex-A76      | #1188873        | ARM64_ERRATUM_1188873       |

| ARM            | Cortex-A76      | #1188873,1418040| ARM64_ERRATUM_1418040       |

| ARM            | Cortex-A76      | #1165522        | ARM64_ERRATUM_1165522       |

| ARM            | Cortex-A76      | #1286807        | ARM64_ERRATUM_1286807       |

| ARM            | Neoverse-N1     | #1188873        | ARM64_ERRATUM_1188873       |

| ARM            | MMU-500         | #841119,#826419 | N/A                         |

| ARM            | Cortex-A76      | #1463225        | ARM64_ERRATUM_1463225       |

| ARM            | Neoverse-N1     | #1188873,1418040| ARM64_ERRATUM_1418040       |

| ARM            | MMU-500         | #841119,826419  | N/A                         |

|                |                 |                 |                             |

| Cavium         | ThunderX ITS    | #22375, #24313  | CAVIUM_ERRATUM_22375        |

| Cavium         | ThunderX ITS    | #22375,24313    | CAVIUM_ERRATUM_22375        |

| Cavium         | ThunderX ITS    | #23144          | CAVIUM_ERRATUM_23144        |

| Cavium         | ThunderX GICv3  | #23154          | CAVIUM_ERRATUM_23154        |

| Cavium         | ThunderX Core   | #27456          | CAVIUM_ERRATUM_27456        |

arch/arm64/Kconfig

+22 −4
Original line number Diff line number Diff line
@@ -476,16 +476,15 @@ config ARM64_ERRATUM_1024718 


	  If unsure, say Y.



config ARM64_ERRATUM_1188873

config ARM64_ERRATUM_1418040

	bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"

	default y

	depends on COMPAT

	select ARM_ARCH_TIMER_OOL_WORKAROUND

	help

	  This option adds a workaround for ARM Cortex-A76/Neoverse-N1

	  erratum 1188873.

	  errata 1188873 and 1418040.



	  Affected Cortex-A76/Neoverse-N1 cores (r0p0, r1p0, r2p0) could

	  Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could

	  cause register corruption when accessing the timer registers

	  from AArch32 userspace.
@@ -521,6 +520,24 @@ config ARM64_ERRATUM_1286807 


	  If unsure, say Y.



config ARM64_ERRATUM_1463225

	bool "Cortex-A76: Software Step might prevent interrupt recognition"

	default y

	help

	  This option adds a workaround for Arm Cortex-A76 erratum 1463225.



	  On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping

	  of a system call instruction (SVC) can prevent recognition of

	  subsequent interrupts when software stepping is disabled in the

	  exception handler of the system call and either kernel debugging

	  is enabled or VHE is in use.



	  Work around the erratum by triggering a dummy step exception

	  when handling a system call from a task that is being stepped

	  in a VHE configuration of the kernel.



	  If unsure, say Y.



config CAVIUM_ERRATUM_22375

	bool "Cavium erratum 22375, 24313"

	default y
@@ -1406,6 +1423,7 @@ config ARM64_MODULE_PLTS 


config ARM64_PSEUDO_NMI

	bool "Support for NMI-like interrupts"

	depends on BROKEN # 1556553607-46531-1-git-send-email-julien.thierry@arm.com

	select CONFIG_ARM_GIC_V3

	help

	  Adds support for mimicking Non-Maskable Interrupts through the use of

arch/arm64/include/asm/cpucaps.h

+3 −2
Original line number Diff line number Diff line
@@ -53,7 +53,7 @@ 
#define ARM64_HAS_STAGE2_FWB			32

#define ARM64_HAS_CRC32				33

#define ARM64_SSBS				34

#define ARM64_WORKAROUND_1188873		35

#define ARM64_WORKAROUND_1418040		35

#define ARM64_HAS_SB				36

#define ARM64_WORKAROUND_1165522		37

#define ARM64_HAS_ADDRESS_AUTH_ARCH		38
@@ -62,7 +62,8 @@ 
#define ARM64_HAS_GENERIC_AUTH_IMP_DEF		41

#define ARM64_HAS_IRQ_PRIO_MASKING		42

#define ARM64_HAS_DCPODP			43

#define ARM64_WORKAROUND_1463225		44



#define ARM64_NCAPS				44

#define ARM64_NCAPS				45



#endif /* __ASM_CPUCAPS_H */

arch/arm64/include/asm/insn.h

+12 −6
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ 
 */

#ifndef	__ASM_INSN_H

#define	__ASM_INSN_H

#include <linux/build_bug.h>

#include <linux/types.h>



/* A64 instructions are always 32 bits. */
@@ -268,16 +269,21 @@ enum aarch64_insn_adr_type { 


#define	__AARCH64_INSN_FUNCS(abbr, mask, val)				\

static __always_inline bool aarch64_insn_is_##abbr(u32 code)		\

{ return (code & (mask)) == (val); } \

{									\

	BUILD_BUG_ON(~(mask) & (val));					\

	return (code & (mask)) == (val);				\

}									\

static __always_inline u32 aarch64_insn_get_##abbr##_value(void)	\

{ return (val); }

{									\

	return (val);							\

}



__AARCH64_INSN_FUNCS(adr,	0x9F000000, 0x10000000)

__AARCH64_INSN_FUNCS(adrp,	0x9F000000, 0x90000000)

__AARCH64_INSN_FUNCS(prfm,	0x3FC00000, 0x39800000)

__AARCH64_INSN_FUNCS(prfm_lit,	0xFF000000, 0xD8000000)

__AARCH64_INSN_FUNCS(str_reg,	0x3FE0EC00, 0x38206800)

__AARCH64_INSN_FUNCS(ldadd,	0x3F20FC00, 0xB8200000)

__AARCH64_INSN_FUNCS(ldadd,	0x3F20FC00, 0x38200000)

__AARCH64_INSN_FUNCS(ldr_reg,	0x3FE0EC00, 0x38606800)

__AARCH64_INSN_FUNCS(ldr_lit,	0xBF000000, 0x18000000)

__AARCH64_INSN_FUNCS(ldrsw_lit,	0xFF000000, 0x98000000)

arch/arm64/kernel/cpu_errata.c

+38 −10
Original line number Diff line number Diff line
@@ -502,6 +502,22 @@ static const struct midr_range arm64_ssb_cpus[] = { 
	{},

};



#ifdef CONFIG_ARM64_ERRATUM_1463225

DEFINE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa);



static bool

has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities *entry,

			       int scope)

{

	u32 midr = read_cpuid_id();

	/* Cortex-A76 r0p0 - r3p1 */

	struct midr_range range = MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1);



	WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());

	return is_midr_in_range(midr, &range) && is_kernel_in_hyp_mode();

}

#endif



static void __maybe_unused

cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused)

{
@@ -682,12 +698,16 @@ static const struct midr_range workaround_clean_cache[] = { 
};

#endif



#ifdef CONFIG_ARM64_ERRATUM_1188873

static const struct midr_range erratum_1188873_list[] = {

	/* Cortex-A76 r0p0 to r2p0 */

	MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),

	/* Neoverse-N1 r0p0 to r2p0 */

	MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 2, 0),

#ifdef CONFIG_ARM64_ERRATUM_1418040

/*

 * - 1188873 affects r0p0 to r2p0

 * - 1418040 affects r0p0 to r3p1

 */

static const struct midr_range erratum_1418040_list[] = {

	/* Cortex-A76 r0p0 to r3p1 */

	MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),

	/* Neoverse-N1 r0p0 to r3p1 */

	MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 3, 1),

	{},

};

#endif
@@ -809,11 +829,11 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		.matches = has_ssbd_mitigation,

		.midr_range_list = arm64_ssb_cpus,

	},

#ifdef CONFIG_ARM64_ERRATUM_1188873

#ifdef CONFIG_ARM64_ERRATUM_1418040

	{

		.desc = "ARM erratum 1188873",

		.capability = ARM64_WORKAROUND_1188873,

		ERRATA_MIDR_RANGE_LIST(erratum_1188873_list),

		.desc = "ARM erratum 1418040",

		.capability = ARM64_WORKAROUND_1418040,

		ERRATA_MIDR_RANGE_LIST(erratum_1418040_list),

	},

#endif

#ifdef CONFIG_ARM64_ERRATUM_1165522
@@ -823,6 +843,14 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		.capability = ARM64_WORKAROUND_1165522,

		ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),

	},

#endif

#ifdef CONFIG_ARM64_ERRATUM_1463225

	{

		.desc = "ARM erratum 1463225",

		.capability = ARM64_WORKAROUND_1463225,

		.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,

		.matches = has_cortex_a76_erratum_1463225,

	},

#endif

	{

	}

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