Commit 0a437d49 authored by Oscar Mateo's avatar Oscar Mateo Committed by Mika Kuoppala
Browse files

drm/i915/icl: Wa_1405779004 



Disable MSC clock gating to prevent data corruption.

BSpec: 19257

v2: Rebased on top of the WA refactoring
v3: Added References (Mika)
v4:
  - Rebased
  - C, not lisp (Chris)
  - A0 only (Mika)

References: HSDES#1405779004
Signed-off-by: default avatarOscar Mateo <oscar.mateo@intel.com>
Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1525814984-20039-10-git-send-email-oscar.mateo@intel.com
parent 908ae051

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -3840,6 +3840,7 @@ enum { 
#define SLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x94d4)

#define  SARBUNIT_CLKGATE_DIS		(1 << 5)

#define  RCCUNIT_CLKGATE_DIS		(1 << 7)

#define  MSCUNIT_CLKGATE_DIS		(1 << 10)



#define SUBSLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x9524)

#define  GWUNIT_CLKGATE_DIS		(1 << 16)

drivers/gpu/drm/i915/intel_workarounds.c

+6 −0
Original line number Diff line number Diff line
@@ -739,6 +739,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv) 
	 */

	I915_WRITE(GAMW_ECO_DEV_RW_IA_REG, I915_READ(GAMW_ECO_DEV_RW_IA_REG) |

					   GAMW_ECO_DEV_CTX_RELOAD_DISABLE);



	/* Wa_1405779004:icl (pre-prod) */

	if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_A0))

		I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,

			   I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |

			   MSCUNIT_CLKGATE_DIS);

}



void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)

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