Commit 0a379e27 authored by Ander Conselvan de Oliveira's avatar Ander Conselvan de Oliveira
Browse files

drm/i915/bxt: Don't set OCL2_LDOFUSE_PWR_DIS bit in phy init sequence 



Hardware engineers confirmed that writing to it has no effect, as implied
by the FIXME comment.

v2: Also remove comment from bxt_ddi_phy_verify_state(). (Imre)
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: default avatarAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1478069096-11209-1-git-send-email-ander.conselvan.de.oliveira@intel.com
parent 3599a91c

drivers/gpu/drm/i915/intel_dpio_phy.c

+0 −21
Original line number Diff line number Diff line
@@ -365,22 +365,6 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv, 
		I915_WRITE(BXT_PORT_CL2CM_DW6(phy), val);

	}



	val = I915_READ(BXT_PORT_CL1CM_DW30(phy));

	val &= ~OCL2_LDOFUSE_PWR_DIS;

	/*

	 * On PHY1 disable power on the second channel, since no port is

	 * connected there. On PHY0 both channels have a port, so leave it

	 * enabled.

	 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should

	 * power down the second channel on PHY0 as well.

	 *

	 * FIXME: Clarify programming of the following, the register is

	 * read-only with bit 6 fixed at 0 at least in stepping A.

	 */

	if (!phy_info->dual_channel)

		val |= OCL2_LDOFUSE_PWR_DIS;

	I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);



	if (phy_info->rcomp_phy != -1) {

		uint32_t grc_code;

		/*
@@ -508,11 +492,6 @@ bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv, 
			   DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN,

			   "BXT_PORT_CL2CM_DW6(%d)", phy);



	/*

	 * TODO: Verify BXT_PORT_CL1CM_DW30 bit OCL2_LDOFUSE_PWR_DIS,

	 * at least on stepping A this bit is read-only and fixed at 0.

	 */



	if (phy_info->rcomp_phy != -1) {

		u32 grc_code = dev_priv->bxt_phy_grc;

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