Commit 0a2a18b7 authored Jan 12, 2009 by Ingo Molnar

x86: change the default cache size to 64 bytes



Right now the generic cacheline size is 128 bytes - that is wasteful
when structures are aligned, as all modern x86 CPUs have an (effective)
cacheline sizes of 64 bytes.

It was set to 128 bytes due to some cacheline aliasing problems on
older P4 systems, but those are many years old and we dont optimize
for them anymore. (They'll still get the 128 bytes cacheline size if
the kernel is specifically built for Pentium 4)

Signed-off-by: Ingo Molnar <mingo@elte.hu>
Acked-by: Arjan van de Ven <arjan@linux.intel.com>

parent 09b3ec73

arch/x86/Kconfig.cpu

+2 −2

Original line number	Diff line number	Diff line
		@@ -307,10 +307,10 @@ config X86_CMPXCHG

		config X86_L1_CACHE_SHIFT
		int
		default "7" if MPENTIUM4 \|\| X86_GENERIC \|\| GENERIC_CPU \|\| MPSC
		default "7" if MPENTIUM4 \|\| MPSC
		default "4" if X86_ELAN \|\| M486 \|\| M386 \|\| MGEODEGX1
		default "5" if MWINCHIP3D \|\| MWINCHIPC6 \|\| MCRUSOE \|\| MEFFICEON \|\| MCYRIXIII \|\| MK6 \|\| MPENTIUMIII \|\| MPENTIUMII \|\| M686 \|\| M586MMX \|\| M586TSC \|\| M586 \|\| MVIAC3_2 \|\| MGEODE_LX
		default "6" if MK7 \|\| MK8 \|\| MPENTIUMM \|\| MCORE2 \|\| MVIAC7
		default "6" if MK7 \|\| MK8 \|\| MPENTIUMM \|\| MCORE2 \|\| MVIAC7 \|\| X86_GENERIC \|\| GENERIC_CPU

		config X86_XADD
		def_bool y

Admin message