drm/nv50-/disp: move DP link training to core and train from supervisor (0a0afd28) · Commits · 戴 / test

drivers/gpu/drm/nouveau/Makefile

+1 −0

Original line number	Diff line number	Diff line
		@@ -159,6 +159,7 @@ nouveau-y += core/engine/disp/nva3.o
		nouveau-y += core/engine/disp/nvd0.o
		nouveau-y += core/engine/disp/nve0.o
		nouveau-y += core/engine/disp/dacnv50.o
		nouveau-y += core/engine/disp/dport.o
		nouveau-y += core/engine/disp/hdanva3.o
		nouveau-y += core/engine/disp/hdanvd0.o
		nouveau-y += core/engine/disp/hdminv84.o

drivers/gpu/drm/nouveau/core/engine/disp/dport.c

0 → 100644

+346 −0

Original line number	Diff line number	Diff line
		/*
		* Copyright 2013 Red Hat Inc.
		*
		* Permission is hereby granted, free of charge, to any person obtaining a
		* copy of this software and associated documentation files (the "Software"),
		* to deal in the Software without restriction, including without limitation
		* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		* and/or sell copies of the Software, and to permit persons to whom the
		* Software is furnished to do so, subject to the following conditions:
		*
		* The above copyright notice and this permission notice shall be included in
		* all copies or substantial portions of the Software.
		*
		* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		* OTHER DEALINGS IN THE SOFTWARE.
		*
		* Authors: Ben Skeggs
		*/

		#include <subdev/bios.h>
		#include <subdev/bios/dcb.h>
		#include <subdev/bios/dp.h>
		#include <subdev/bios/init.h>
		#include <subdev/i2c.h>

		#include <engine/disp.h>

		#include "dport.h"

		#define DBG(fmt, args...) nv_debug(dp->disp, "DP:%04x:%04x: " fmt, \
		dp->outp->hasht, dp->outp->hashm, ##args)
		#define ERR(fmt, args...) nv_error(dp->disp, "DP:%04x:%04x: " fmt, \
		dp->outp->hasht, dp->outp->hashm, ##args)

		/******************************************************************************
		* link training
		*****************************************************************************/
		struct dp_state {
		const struct nouveau_dp_func *func;
		struct nouveau_disp *disp;
		struct dcb_output *outp;
		struct nvbios_dpout info;
		u8 version;
		struct nouveau_i2c_port *aux;
		int head;
		u8 dpcd[4];
		int link_nr;
		u32 link_bw;
		u8 stat[6];
		u8 conf[4];
		};

		static int
		dp_set_link_config(struct dp_state *dp)
		{
		struct nouveau_disp *disp = dp->disp;
		struct nouveau_bios *bios = nouveau_bios(disp);
		struct nvbios_init init = {
		.subdev = nv_subdev(dp->disp),
		.bios = bios,
		.offset = 0x0000,
		.outp = dp->outp,
		.crtc = dp->head,
		.execute = 1,
		};
		u32 lnkcmp;
		u8 sink[2];

		DBG("%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw);

		/* set desired link configuration on the sink */
		sink[0] = dp->link_bw / 27000;
		sink[1] = dp->link_nr;
		if (dp->dpcd[DPCD_RC02] & DPCD_RC02_ENHANCED_FRAME_CAP)
		sink[1] \|= DPCD_LC01_ENHANCED_FRAME_EN;

		nv_wraux(dp->aux, DPCD_LC00, sink, 2);

		/* set desired link configuration on the source */
		if ((lnkcmp = dp->info.lnkcmp)) {
		if (dp->version < 0x30) {
		while ((dp->link_bw / 10) < nv_ro16(bios, lnkcmp))
		lnkcmp += 4;
		init.offset = nv_ro16(bios, lnkcmp + 2);
		} else {
		while ((dp->link_bw / 27000) < nv_ro08(bios, lnkcmp))
		lnkcmp += 3;
		init.offset = nv_ro16(bios, lnkcmp + 1);
		}

		nvbios_exec(&init);
		}

		return dp->func->lnk_ctl(dp->disp, dp->outp, dp->head,
		dp->link_nr, dp->link_bw / 27000,
		dp->dpcd[DPCD_RC02] &
		DPCD_RC02_ENHANCED_FRAME_CAP);
		}

		static void
		dp_set_training_pattern(struct dp_state *dp, u8 pattern)
		{
		u8 sink_tp;

		DBG("training pattern %d\n", pattern);
		dp->func->pattern(dp->disp, dp->outp, dp->head, pattern);

		nv_rdaux(dp->aux, DPCD_LC02, &sink_tp, 1);
		sink_tp &= ~DPCD_LC02_TRAINING_PATTERN_SET;
		sink_tp \|= pattern;
		nv_wraux(dp->aux, DPCD_LC02, &sink_tp, 1);
		}

		static int
		dp_link_train_commit(struct dp_state *dp)
		{
		int i;

		for (i = 0; i < dp->link_nr; i++) {
		u8 lane = (dp->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf;
		u8 lpre = (lane & 0x0c) >> 2;
		u8 lvsw = (lane & 0x03) >> 0;

		dp->conf[i] = (lpre << 3) \| lvsw;
		if (lvsw == 3)
		dp->conf[i] \|= DPCD_LC03_MAX_SWING_REACHED;
		if (lpre == 3)
		dp->conf[i] \|= DPCD_LC03_MAX_PRE_EMPHASIS_REACHED;

		DBG("config lane %d %02x\n", i, dp->conf[i]);
		dp->func->drv_ctl(dp->disp, dp->outp, dp->head, i, lvsw, lpre);
		}

		return nv_wraux(dp->aux, DPCD_LC03(0), dp->conf, 4);
		}

		static int
		dp_link_train_update(struct dp_state *dp, u32 delay)
		{
		int ret;

		udelay(delay);

		ret = nv_rdaux(dp->aux, DPCD_LS02, dp->stat, 6);
		if (ret)
		return ret;

		DBG("status %*ph\n", 6, dp->stat);
		return 0;
		}

		static int
		dp_link_train_cr(struct dp_state *dp)
		{
		bool cr_done = false, abort = false;
		int voltage = dp->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET;
		int tries = 0, i;

		dp_set_training_pattern(dp, 1);

		do {
		if (dp_link_train_commit(dp) \|\|
		dp_link_train_update(dp, 100))
		break;

		cr_done = true;
		for (i = 0; i < dp->link_nr; i++) {
		u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
		if (!(lane & DPCD_LS02_LANE0_CR_DONE)) {
		cr_done = false;
		if (dp->conf[i] & DPCD_LC03_MAX_SWING_REACHED)
		abort = true;
		break;
		}
		}

		if ((dp->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET) != voltage) {
		voltage = dp->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET;
		tries = 0;
		}
		} while (!cr_done && !abort && ++tries < 5);

		return cr_done ? 0 : -1;
		}

		static int
		dp_link_train_eq(struct dp_state *dp)
		{
		bool eq_done, cr_done = true;
		int tries = 0, i;

		dp_set_training_pattern(dp, 2);

		do {
		if (dp_link_train_update(dp, 400))
		break;

		eq_done = !!(dp->stat[2] & DPCD_LS04_INTERLANE_ALIGN_DONE);
		for (i = 0; i < dp->link_nr && eq_done; i++) {
		u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
		if (!(lane & DPCD_LS02_LANE0_CR_DONE))
		cr_done = false;
		if (!(lane & DPCD_LS02_LANE0_CHANNEL_EQ_DONE) \|\|
		!(lane & DPCD_LS02_LANE0_SYMBOL_LOCKED))
		eq_done = false;
		}

		if (dp_link_train_commit(dp))
		break;
		} while (!eq_done && cr_done && ++tries <= 5);

		return eq_done ? 0 : -1;
		}

		static void
		dp_link_train_init(struct dp_state *dp, bool spread)
		{
		struct nvbios_init init = {
		.subdev = nv_subdev(dp->disp),
		.bios = nouveau_bios(dp->disp),
		.outp = dp->outp,
		.crtc = dp->head,
		.execute = 1,
		};

		/* set desired spread */
		if (spread)
		init.offset = dp->info.script[2];
		else
		init.offset = dp->info.script[3];
		nvbios_exec(&init);

		/* pre-train script */
		init.offset = dp->info.script[0];
		nvbios_exec(&init);
		}

		static void
		dp_link_train_fini(struct dp_state *dp)
		{
		struct nvbios_init init = {
		.subdev = nv_subdev(dp->disp),
		.bios = nouveau_bios(dp->disp),
		.outp = dp->outp,
		.crtc = dp->head,
		.execute = 1,
		};

		/* post-train script */
		init.offset = dp->info.script[1],
		nvbios_exec(&init);
		}

		int
		nouveau_dp_train(struct nouveau_disp disp, const struct nouveau_dp_func func,
		struct dcb_output *outp, int head, u32 datarate)
		{
		struct nouveau_bios *bios = nouveau_bios(disp);
		struct nouveau_i2c *i2c = nouveau_i2c(disp);
		struct dp_state _dp = {
		.disp = disp,
		.func = func,
		.outp = outp,
		.head = head,
		}, *dp = &_dp;
		const u32 bw_list[] = { 270000, 162000, 0 };
		const u32 *link_bw = bw_list;
		u8 hdr, cnt, len;
		u32 data;
		int ret;

		/* find the bios displayport data relevant to this output */
		data = nvbios_dpout_match(bios, outp->hasht, outp->hashm, &dp->version,
		&hdr, &cnt, &len, &dp->info);
		if (!data) {
		ERR("bios data not found\n");
		return -EINVAL;
		}

		/* acquire the aux channel and fetch some info about the display */
		if (outp->location)
		dp->aux = i2c->find_type(i2c, NV_I2C_TYPE_EXTAUX(outp->extdev));
		else
		dp->aux = i2c->find(i2c, NV_I2C_TYPE_DCBI2C(outp->i2c_index));
		if (!dp->aux) {
		ERR("no aux channel?!\n");
		return -ENODEV;
		}

		ret = nv_rdaux(dp->aux, 0x00000, dp->dpcd, sizeof(dp->dpcd));
		if (ret) {
		ERR("failed to read DPCD\n");
		return ret;
		}

		/* adjust required bandwidth for 8B/10B coding overhead */
		datarate = (datarate / 8) * 10;

		/* enable down-spreading and execute pre-train script from vbios */
		dp_link_train_init(dp, dp->dpcd[3] & 0x01);

		/* start off at highest link rate supported by encoder and display */
		while (link_bw > (dp->dpcd[1] 27000))
		link_bw++;

		while (link_bw[0]) {
		/* find minimum required lane count at this link rate */
		dp->link_nr = dp->dpcd[2] & DPCD_RC02_MAX_LANE_COUNT;
		while ((dp->link_nr >> 1) * link_bw[0] > datarate)
		dp->link_nr >>= 1;

		/* drop link rate to minimum with this lane count */
		while ((link_bw[1] * dp->link_nr) > datarate)
		link_bw++;
		dp->link_bw = link_bw[0];

		/* program selected link configuration */
		ret = dp_set_link_config(dp);
		if (ret == 0) {
		/* attempt to train the link at this configuration */
		memset(dp->stat, 0x00, sizeof(dp->stat));
		if (!dp_link_train_cr(dp) &&
		!dp_link_train_eq(dp))
		break;
		} else
		if (ret >= 1) {
		/* dp_set_link_config() handled training */
		break;
		}

		/* retry at lower rate */
		link_bw++;
		}

		/* finish link training */
		dp_set_training_pattern(dp, 0);

		/* execute post-train script from vbios */
		dp_link_train_fini(dp);
		return true;
		}

drivers/gpu/drm/nouveau/core/engine/disp/dport.h

0 → 100644

+77 −0

Original line number	Diff line number	Diff line
		#ifndef __NVKM_DISP_DPORT_H__
		#define __NVKM_DISP_DPORT_H__

		/* DPCD Receiver Capabilities */
		#define DPCD_RC00 0x00000
		#define DPCD_RC00_DPCD_REV 0xff
		#define DPCD_RC01 0x00001
		#define DPCD_RC01_MAX_LINK_RATE 0xff
		#define DPCD_RC02 0x00002
		#define DPCD_RC02_ENHANCED_FRAME_CAP 0x80
		#define DPCD_RC02_MAX_LANE_COUNT 0x1f
		#define DPCD_RC03 0x00003
		#define DPCD_RC03_MAX_DOWNSPREAD 0x01

		/* DPCD Link Configuration */
		#define DPCD_LC00 0x00100
		#define DPCD_LC00_LINK_BW_SET 0xff
		#define DPCD_LC01 0x00101
		#define DPCD_LC01_ENHANCED_FRAME_EN 0x80
		#define DPCD_LC01_LANE_COUNT_SET 0x1f
		#define DPCD_LC02 0x00102
		#define DPCD_LC02_TRAINING_PATTERN_SET 0x03
		#define DPCD_LC03(l) ((l) + 0x00103)
		#define DPCD_LC03_MAX_PRE_EMPHASIS_REACHED 0x20
		#define DPCD_LC03_PRE_EMPHASIS_SET 0x18
		#define DPCD_LC03_MAX_SWING_REACHED 0x04
		#define DPCD_LC03_VOLTAGE_SWING_SET 0x03

		/* DPCD Link/Sink Status */
		#define DPCD_LS02 0x00202
		#define DPCD_LS02_LANE1_SYMBOL_LOCKED 0x40
		#define DPCD_LS02_LANE1_CHANNEL_EQ_DONE 0x20
		#define DPCD_LS02_LANE1_CR_DONE 0x10
		#define DPCD_LS02_LANE0_SYMBOL_LOCKED 0x04
		#define DPCD_LS02_LANE0_CHANNEL_EQ_DONE 0x02
		#define DPCD_LS02_LANE0_CR_DONE 0x01
		#define DPCD_LS03 0x00203
		#define DPCD_LS03_LANE3_SYMBOL_LOCKED 0x40
		#define DPCD_LS03_LANE3_CHANNEL_EQ_DONE 0x20
		#define DPCD_LS03_LANE3_CR_DONE 0x10
		#define DPCD_LS03_LANE2_SYMBOL_LOCKED 0x04
		#define DPCD_LS03_LANE2_CHANNEL_EQ_DONE 0x02
		#define DPCD_LS03_LANE2_CR_DONE 0x01
		#define DPCD_LS04 0x00204
		#define DPCD_LS04_LINK_STATUS_UPDATED 0x80
		#define DPCD_LS04_DOWNSTREAM_PORT_STATUS_CHANGED 0x40
		#define DPCD_LS04_INTERLANE_ALIGN_DONE 0x01
		#define DPCD_LS06 0x00206
		#define DPCD_LS06_LANE1_PRE_EMPHASIS 0xc0
		#define DPCD_LS06_LANE1_VOLTAGE_SWING 0x30
		#define DPCD_LS06_LANE0_PRE_EMPHASIS 0x0c
		#define DPCD_LS06_LANE0_VOLTAGE_SWING 0x03
		#define DPCD_LS07 0x00207
		#define DPCD_LS07_LANE3_PRE_EMPHASIS 0xc0
		#define DPCD_LS07_LANE3_VOLTAGE_SWING 0x30
		#define DPCD_LS07_LANE2_PRE_EMPHASIS 0x0c
		#define DPCD_LS07_LANE2_VOLTAGE_SWING 0x03

		struct nouveau_disp;
		struct dcb_output;

		struct nouveau_dp_func {
		int (pattern)(struct nouveau_disp , struct dcb_output *,
		int head, int pattern);
		int (lnk_ctl)(struct nouveau_disp , struct dcb_output *, int head,
		int link_nr, int link_bw, bool enh_frame);
		int (drv_ctl)(struct nouveau_disp , struct dcb_output *, int head,
		int lane, int swing, int preem);
		};

		extern const struct nouveau_dp_func nv94_sor_dp_func;
		extern const struct nouveau_dp_func nvd0_sor_dp_func;

		int nouveau_dp_train(struct nouveau_disp , const struct nouveau_dp_func ,
		struct dcb_output *, int, u32);

		#endif

drivers/gpu/drm/nouveau/core/engine/disp/nv50.c

+24 −5

Original line number	Diff line number	Diff line
		@@ -911,7 +911,7 @@ exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk,
		}

		data = nvbios_ocfg_match(bios, data, conf, &ver, &hdr, &cnt, &len, &info2);
		if (data) {
		if (data && id < 0xff) {
		data = nvbios_oclk_match(bios, info2.clkcmp[id], pclk);
		if (data) {
		struct nvbios_init init = {
		@@ -1078,8 +1078,28 @@ nv50_disp_intr_unk20(struct nv50_disp_priv *priv, u32 super)
		head = ffs((super & 0x00000180) >> 7) - 1;
		if (head >= 0) {
		u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
		u32 conf = exec_clkcmp(priv, head, 0, pclk, &outp);
		u32 conf = exec_clkcmp(priv, head, 0xff, pclk, &outp);
		if (conf != ~0) {
		if (outp.location == 0 && outp.type == DCB_OUTPUT_DP) {
		u32 soff = (ffs(outp.or) - 1) * 0x08;
		u32 ctrl = nv_rd32(priv, 0x610798 + soff);
		u32 datarate;

		switch ((ctrl & 0x000f0000) >> 16) {
		case 6: datarate = pclk * 30 / 8; break;
		case 5: datarate = pclk * 24 / 8; break;
		case 2:
		default:
		datarate = pclk * 18 / 8;
		break;
		}

		nouveau_dp_train(&priv->base, priv->sor.dp,
		&outp, head, datarate);
		}

		exec_clkcmp(priv, head, 0, pclk, &outp);

		if (outp.type == DCB_OUTPUT_ANALOG) {
		addr = 0x614280 + (ffs(outp.or) - 1) * 0x800;
		mask = 0xffffffff;
		@@ -1128,11 +1148,10 @@ nv50_disp_intr_unk40(struct nv50_disp_priv *priv, u32 super)
		if (head >= 0) {
		struct dcb_output outp;
		u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
		if (exec_clkcmp(priv, head, 1, pclk, &outp) != ~0) {
		if (outp.type == DCB_OUTPUT_TMDS)
		if (exec_clkcmp(priv, head, 1, pclk, &outp) != ~0)
		if (outp.location == 0 && outp.type == DCB_OUTPUT_TMDS)
		nv50_disp_intr_unk40_tmds(priv, &outp);
		}
		}

		nv_wr32(priv, 0x610030, 0x80000000);
		}

drivers/gpu/drm/nouveau/core/engine/disp/nv50.h

+2 −16

Original line number	Diff line number	Diff line
		@@ -10,7 +10,7 @@
		#include <engine/dmaobj.h>
		#include <engine/disp.h>

		struct dcb_output;
		#include "dport.h"

		struct nv50_disp_priv {
		struct nouveau_disp base;
		@@ -32,22 +32,8 @@ struct nv50_disp_priv {
		int (power)(struct nv50_disp_priv , int sor, u32 data);
		int (hda_eld)(struct nv50_disp_priv , int sor, u8 *, u32);
		int (hdmi)(struct nv50_disp_priv , int head, int sor, u32);
		int (dp_train_init)(struct nv50_disp_priv , int sor, int link,
		int head, u16 type, u16 mask, u32 data,
		struct dcb_output *);
		int (dp_train_fini)(struct nv50_disp_priv , int sor, int link,
		int head, u16 type, u16 mask, u32 data,
		struct dcb_output *);
		int (dp_train)(struct nv50_disp_priv , int sor, int link,
		u16 type, u16 mask, u32 data,
		struct dcb_output *);
		int (dp_lnkctl)(struct nv50_disp_priv , int sor, int link,
		int head, u16 type, u16 mask, u32 data,
		struct dcb_output *);
		int (dp_drvctl)(struct nv50_disp_priv , int sor, int link,
		int lane, u16 type, u16 mask, u32 data,
		struct dcb_output *);
		u32 lvdsconf;
		const struct nouveau_dp_func *dp;
		} sor;
		};

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