Commit 09da89ab authored by Guenter Roeck's avatar Guenter Roeck Committed by Wim Van Sebroeck
Browse files

watchdog: sp5100_tco: Enable watchdog on Family 17h devices if disabled 



On Family 17h (Ryzen) devices, the WatchdogTmrEn bit of PmDecodeEn not only
enables watchdog memory decoding at 0xfeb00000, it also enables the
watchdog hardware itself. Use this information to enable the watchdog if
it is not already enabled.

Cc: Jan Kiszka <jan.kiszka@siemens.com>
Tested-by: default avatarJan Kiszka <jan.kiszka@siemens.com>
Link: https://lore.kernel.org/r/20200910163109.235136-2-linux@roeck-us.net


Signed-off-by: default avatarGuenter Roeck <linux@roeck-us.net>
Signed-off-by: default avatarWim Van Sebroeck <wim@linux-watchdog.org>
parent 08c619b4

drivers/watchdog/sp5100_tco.c

+18 −0
Original line number Diff line number Diff line
@@ -17,6 +17,12 @@ 
 *	    AMD Publication 51192 "AMD Bolton FCH Register Reference Guide"

 *	    AMD Publication 52740 "BIOS and Kernel Developer’s Guide (BKDG)

 *				for AMD Family 16h Models 30h-3Fh Processors"

 *	    AMD Publication 55570-B1-PUB "Processor Programming Reference (PPR)

 *				for AMD Family 17h Model 18h, Revision B1

 *				Processors (PUB)

 *	    AMD Publication 55772-A1-PUB "Processor Programming Reference (PPR)

 *				for AMD Family 17h Model 20h, Revision A1

 *				Processors (PUB)

 */



/*
@@ -241,6 +247,18 @@ static int sp5100_tco_setupdevice(struct device *dev, 
		break;

	case efch:

		dev_name = SB800_DEVNAME;

		/*

		 * On Family 17h devices, the EFCH_PM_DECODEEN_WDT_TMREN bit of

		 * EFCH_PM_DECODEEN not only enables the EFCH_PM_WDT_ADDR memory

		 * region, it also enables the watchdog itself.

		 */

		if (boot_cpu_data.x86 == 0x17) {

			val = sp5100_tco_read_pm_reg8(EFCH_PM_DECODEEN);

			if (!(val & EFCH_PM_DECODEEN_WDT_TMREN)) {

				sp5100_tco_update_pm_reg8(EFCH_PM_DECODEEN, 0xff,

							  EFCH_PM_DECODEEN_WDT_TMREN);

			}

		}

		val = sp5100_tco_read_pm_reg8(EFCH_PM_DECODEEN);

		if (val & EFCH_PM_DECODEEN_WDT_TMREN)

			mmio_addr = EFCH_PM_WDT_ADDR;

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