Commit 09c0998e authored by Mark Brown's avatar Mark Brown
Browse files

Merge tag 'spi-v3.15' into spi-linus 

spi: Updates for v3.15

A busy release for both cleanups and new drivers this time along with
further factoring out of replicated code into the core:

 - Provide support in the core for DMA mapping transfers - essentially
   all drivers weren't implementing this properly, now there's no
   excuse.
 - Dual and quad mode support for spidev.
 - Fix handling of cs_change in the generic implementation.
 - Remove the S3C_DMA code from the s3c64xx driver now that all the
   platforms using it have been converted to dmaengine.
 - Lots of improvements to the Renesas SPI controllers.
 - Drivers for Allwinner A10 and A31, Qualcomm QUP and Xylinx xtfpga.
 - Removal of the bitrotted ti-ssp driver.

# gpg: Signature made Mon 31 Mar 2014 12:03:09 BST using RSA key ID 7EA229BD
# gpg: Good signature from "Mark Brown <broonie@sirena.org.uk>"
# gpg:                 aka "Mark Brown <broonie@debian.org>"
# gpg:                 aka "Mark Brown <broonie@kernel.org>"
# gpg:                 aka "Mark Brown <broonie@tardis.ed.ac.uk>"
# gpg:                 aka "Mark Brown <broonie@linaro.org>"
# gpg:                 aka "Mark Brown <Mark.Brown@linaro.org>"
parents 455c6fdb 45b15d98

Documentation/devicetree/bindings/spi/efm32-spi.txt

+4 −4
Original line number Diff line number Diff line
@@ -3,24 +3,24 @@ 
Required properties:

- #address-cells: see spi-bus.txt

- #size-cells: see spi-bus.txt

- compatible: should be "efm32,spi"

- compatible: should be "energymicro,efm32-spi"

- reg: Offset and length of the register set for the controller

- interrupts: pair specifying rx and tx irq

- clocks: phandle to the spi clock

- cs-gpios: see spi-bus.txt

- location: Value to write to the ROUTE register's LOCATION bitfield to configure the pinmux for the device, see datasheet for values.

- efm32,location: Value to write to the ROUTE register's LOCATION bitfield to configure the pinmux for the device, see datasheet for values.



Example:



spi1: spi@0x4000c400 { /* USART1 */

	#address-cells = <1>;

	#size-cells = <0>;

	compatible = "efm32,spi";

	compatible = "energymicro,efm32-spi";

	reg = <0x4000c400 0x400>;

	interrupts = <15 16>;

	clocks = <&cmu 20>;

	cs-gpios = <&gpio 51 1>; // D3

	location = <1>;

	efm32,location = <1>;

	status = "ok";



	ks8851@0 {

Documentation/devicetree/bindings/spi/qcom,spi-qup.txt

0 → 100644
+85 −0
Original line number Diff line number Diff line 
Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)



The QUP core is an AHB slave that provides a common data path (an output FIFO

and an input FIFO) for serial peripheral interface (SPI) mini-core.



SPI in master mode supports up to 50MHz, up to four chip selects, programmable

data path from 4 bits to 32 bits and numerous protocol variants.



Required properties:

- compatible:     Should contain "qcom,spi-qup-v2.1.1" or "qcom,spi-qup-v2.2.1"

- reg:            Should contain base register location and length

- interrupts:     Interrupt number used by this controller



- clocks:         Should contain the core clock and the AHB clock.

- clock-names:    Should be "core" for the core clock and "iface" for the

                  AHB clock.



- #address-cells: Number of cells required to define a chip select

                  address on the SPI bus. Should be set to 1.

- #size-cells:    Should be zero.



Optional properties:

- spi-max-frequency: Specifies maximum SPI clock frequency,

                     Units - Hz. Definition as per

                     Documentation/devicetree/bindings/spi/spi-bus.txt



SPI slave nodes must be children of the SPI master node and can contain

properties described in Documentation/devicetree/bindings/spi/spi-bus.txt



Example:



	spi_8: spi@f9964000 { /* BLSP2 QUP2 */



		compatible = "qcom,spi-qup-v2";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0xf9964000 0x1000>;

		interrupts = <0 102 0>;

		spi-max-frequency = <19200000>;



		clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;

		clock-names = "core", "iface";



		pinctrl-names = "default";

		pinctrl-0 = <&spi8_default>;



		device@0 {

			compatible = "arm,pl022-dummy";

			#address-cells = <1>;

			#size-cells = <1>;

			reg = <0>; /* Chip select 0 */

			spi-max-frequency = <19200000>;

			spi-cpol;

		};



		device@1 {

			compatible = "arm,pl022-dummy";

			#address-cells = <1>;

			#size-cells = <1>;

			reg = <1>; /* Chip select 1 */

			spi-max-frequency = <9600000>;

			spi-cpha;

		};



		device@2 {

			compatible = "arm,pl022-dummy";

			#address-cells = <1>;

			#size-cells = <1>;

			reg = <2>; /* Chip select 2 */

			spi-max-frequency = <19200000>;

			spi-cpol;

			spi-cpha;

		};



		device@3 {

			compatible = "arm,pl022-dummy";

			#address-cells = <1>;

			#size-cells = <1>;

			reg = <3>; /* Chip select 3 */

			spi-max-frequency = <19200000>;

			spi-cpol;

			spi-cpha;

			spi-cs-high;

		};

	};

Documentation/devicetree/bindings/spi/sh-hspi.txt

+25 −3
Original line number Diff line number Diff line 
Renesas HSPI.



Required properties:

- compatible : 	"renesas,hspi"

- compatible       : "renesas,hspi-<soctype>", "renesas,hspi" as fallback.

		     Examples with soctypes are:

		       - "renesas,hspi-r8a7778" (R-Car M1)

		       - "renesas,hspi-r8a7779" (R-Car H1)

- reg              : Offset and length of the register set for the device

- interrupts : interrupt line used by HSPI

- interrupt-parent : The phandle for the interrupt controller that

		     services interrupts for this device

- interrupts       : Interrupt specifier

- #address-cells   : Must be <1>

- #size-cells      : Must be <0>



Pinctrl properties might be needed, too.  See

Documentation/devicetree/bindings/pinctrl/renesas,*.



Example:



	hspi0: spi@fffc7000 {

		compatible = "renesas,hspi-r8a7778", "renesas,hspi";

		reg = <0xfffc7000 0x18>;

		interrupt-parent = <&gic>;

		interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;

		#address-cells = <1>;

		#size-cells = <0>;

		status = "disabled";

	};

Documentation/devicetree/bindings/spi/sh-msiof.txt

+35 −7
Original line number Diff line number Diff line 
Renesas MSIOF spi controller



Required properties:

- compatible : 	"renesas,sh-msiof" for SuperH or

		"renesas,sh-mobile-msiof" for SH Mobile series

- compatible           : "renesas,msiof-<soctype>" for SoCs,

			 "renesas,sh-msiof" for SuperH, or

			 "renesas,sh-mobile-msiof" for SH Mobile series.

			 Examples with soctypes are:

			 "renesas,msiof-r8a7790" (R-Car H2)

			 "renesas,msiof-r8a7791" (R-Car M2)

- reg                  : Offset and length of the register set for the device

- interrupts : interrupt line used by MSIOF

- interrupt-parent     : The phandle for the interrupt controller that

			 services interrupts for this device

- interrupts           : Interrupt specifier

- #address-cells       : Must be <1>

- #size-cells          : Must be <0>



Optional properties:

- num-cs		: total number of chip-selects

- clocks               : Must contain a reference to the functional clock.

- num-cs               : Total number of chip-selects (default is 1)



Optional properties, deprecated for soctype-specific bindings:

- renesas,tx-fifo-size : Overrides the default tx fifo size given in words

			 (default is 64)

- renesas,rx-fifo-size : Overrides the default rx fifo size given in words

			 (default is 64, or 256 on R-Car H2 and M2)



Pinctrl properties might be needed, too.  See

Documentation/devicetree/bindings/pinctrl/renesas,*.



Example:



	msiof0: spi@e6e20000 {

		compatible = "renesas,msiof-r8a7791";

		reg = <0 0xe6e20000 0 0x0064>;

		interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;

		#address-cells = <1>;

		#size-cells = <0>;

		status = "disabled";

	};

Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt

+2 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ Required properties: 
- pinctrl-names: must contain a "default" entry.

- spi-num-chipselects : the number of the chipselect signals.

- bus-num : the slave chip chipselect signal number.

- big-endian : if DSPI modudle is big endian, the bool will be set in node.

Example:



dspi0@4002c000 {
@@ -24,6 +25,7 @@ dspi0@4002c000 { 
	bus-num = <0>;

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_dspi0_1>;

	big-endian;

	status = "okay";



	sflash: at26df081a@0 {

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