Commit 09a32cb7 authored by Tvrtko Ursulin's avatar Tvrtko Ursulin
Browse files

drm/i915: Make GuC GGTT reservation work on ggtt 



These functions operate on ggtt so make them take that directly as
parameter.

At the same time move the USES_GUC conditional down to
intel_guc_reserve_ggtt_top for symmetry with
intel_guc_reserved_gtt_size.

v2:
 * Rename and move functions to be static in i915_gem_gtt.c (Michal)

v3:
 * Add comment explaining reason for reservation, add assert and fix
   error message. (Michal)

v4:
 * Fix checkpatch error.

Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Reviewed-by: default avatarMichal Wajdeczko <michal.wajdeczko@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190611122350.15060-1-tvrtko.ursulin@linux.intel.com
parent 9937e16b

drivers/gpu/drm/i915/i915_gem_gtt.c

+36 −7
Original line number Diff line number Diff line
@@ -2808,6 +2808,32 @@ static void fini_aliasing_ppgtt(struct drm_i915_private *i915) 
	ggtt->vm.vma_ops.unbind_vma = ggtt_unbind_vma;

}



static int ggtt_reserve_guc_top(struct i915_ggtt *ggtt)

{

	u64 size;

	int ret;



	if (!USES_GUC(ggtt->vm.i915))

		return 0;



	GEM_BUG_ON(ggtt->vm.total <= GUC_GGTT_TOP);

	size = ggtt->vm.total - GUC_GGTT_TOP;



	ret = i915_gem_gtt_reserve(&ggtt->vm, &ggtt->uc_fw, size,

				   GUC_GGTT_TOP, I915_COLOR_UNEVICTABLE,

				   PIN_NOEVICT);

	if (ret)

		DRM_DEBUG_DRIVER("Failed to reserve top of GGTT for GuC\n");



	return ret;

}



static void ggtt_release_guc_top(struct i915_ggtt *ggtt)

{

	if (drm_mm_node_allocated(&ggtt->uc_fw))

		drm_mm_remove_node(&ggtt->uc_fw);

}



int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)

{

	/* Let GEM Manage all of the aperture.
@@ -2845,11 +2871,14 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv) 
	if (ret)

		return ret;



	if (USES_GUC(dev_priv)) {

		ret = intel_guc_reserve_ggtt_top(&dev_priv->guc);

	/*

	 * The upper portion of the GuC address space has a sizeable hole

	 * (several MB) that is inaccessible by GuC. Reserve this range within

	 * GGTT as it can comfortably hold GuC/HuC firmware images.

	 */

	ret = ggtt_reserve_guc_top(ggtt);

	if (ret)

		goto err_reserve;

	}



	/* Clear any non-preallocated blocks */

	drm_mm_for_each_hole(entry, &ggtt->vm.mm, hole_start, hole_end) {
@@ -2871,7 +2900,7 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv) 
	return 0;



err_appgtt:

	intel_guc_release_ggtt_top(&dev_priv->guc);

	ggtt_release_guc_top(ggtt);

err_reserve:

	drm_mm_remove_node(&ggtt->error_capture);

	return ret;
@@ -2898,7 +2927,7 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv) 
	if (drm_mm_node_allocated(&ggtt->error_capture))

		drm_mm_remove_node(&ggtt->error_capture);



	intel_guc_release_ggtt_top(&dev_priv->guc);

	ggtt_release_guc_top(ggtt);



	if (drm_mm_initialized(&ggtt->vm.mm)) {

		intel_vgt_deballoon(dev_priv);

drivers/gpu/drm/i915/intel_guc.c

+0 −27
Original line number Diff line number Diff line
@@ -685,30 +685,3 @@ err: 
	i915_gem_object_put(obj);

	return vma;

}
 


int intel_guc_reserve_ggtt_top(struct intel_guc *guc)

{

	struct drm_i915_private *i915 = guc_to_i915(guc);

	struct i915_ggtt *ggtt = &i915->ggtt;

	u64 size;

	int ret;



	size = ggtt->vm.total - GUC_GGTT_TOP;



	ret = i915_gem_gtt_reserve(&ggtt->vm, &ggtt->uc_fw, size,

				   GUC_GGTT_TOP, I915_COLOR_UNEVICTABLE,

				   PIN_NOEVICT);

	if (ret)

		DRM_DEBUG_DRIVER("GuC: failed to reserve top of ggtt\n");



	return ret;

}



void intel_guc_release_ggtt_top(struct intel_guc *guc)

{

	struct drm_i915_private *i915 = guc_to_i915(guc);

	struct i915_ggtt *ggtt = &i915->ggtt;



	if (drm_mm_node_allocated(&ggtt->uc_fw))

		drm_mm_remove_node(&ggtt->uc_fw);

}

drivers/gpu/drm/i915/intel_guc.h

+0 −2
Original line number Diff line number Diff line
@@ -172,8 +172,6 @@ int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset); 
int intel_guc_suspend(struct intel_guc *guc);

int intel_guc_resume(struct intel_guc *guc);

struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);

int intel_guc_reserve_ggtt_top(struct intel_guc *guc);

void intel_guc_release_ggtt_top(struct intel_guc *guc);



static inline bool intel_guc_is_loaded(struct intel_guc *guc)

{

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