Commit 09a31a7e authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mips_5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux 

Pull MIPS updates from Thomas Bogendoerfer:

 - removed support for PNX833x alias NXT_STB22x

 - included Ingenic SoC support into generic MIPS kernels

 - added support for new Ingenic SoCs

 - converted workaround selection to use Kconfig

 - replaced old boot mem functions by memblock_*

 - enabled COP2 usage in kernel for Loongson64 to make use
   of 16byte load/stores possible

 - cleanups and fixes

* tag 'mips_5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (92 commits)
  MIPS: DEC: Restore bootmem reservation for firmware working memory area
  MIPS: dec: fix section mismatch
  bcm963xx_tag.h: fix duplicated word
  mips: ralink: enable zboot support
  MIPS: ingenic: Remove CPU_SUPPORTS_HUGEPAGES
  MIPS: cpu-probe: remove MIPS_CPU_BP_GHIST option bit
  MIPS: cpu-probe: introduce exclusive R3k CPU probe
  MIPS: cpu-probe: move fpu probing/handling into its own file
  MIPS: replace add_memory_region with memblock
  MIPS: Loongson64: Clean up numa.c
  MIPS: Loongson64: Select SMP in Kconfig to avoid build error
  mips: octeon: Add Ubiquiti E200 and E220 boards
  MIPS: SGI-IP28: disable use of ll/sc in kernel
  MIPS: tx49xx: move tx4939_add_memory_regions into only user
  MIPS: pgtable: Remove used PAGE_USERIO define
  MIPS: alchemy: Share prom_init implementation
  MIPS: alchemy: Fix build breakage, if TOUCHSCREEN_WM97XX is disabled
  MIPS: process: include exec.h header in process.c
  MIPS: process: Add prototype for function arch_dup_task_struct
  MIPS: idle: Add prototype for function check_wait
  ...
parents 847d4287 cf3af0a4

Documentation/devicetree/bindings/mips/ingenic/devices.yaml

+5 −0
Original line number Diff line number Diff line
@@ -47,4 +47,9 @@ properties: 
        items:

          - const: yna,cu1830-neo

          - const: ingenic,x1830



      - description: YSH & ATIL General Board, CU2000 Module with Neo Backplane

        items:

          - const: yna,cu2000-neo

          - const: ingenic,x2000e

...

MAINTAINERS

+3 −2
Original line number Diff line number Diff line
@@ -8675,8 +8675,9 @@ INGENIC JZ47xx SoCs 
M:	Paul Cercueil <paul@crapouillou.net>

S:	Maintained

F:	arch/mips/boot/dts/ingenic/

F:	arch/mips/include/asm/mach-jz4740/

F:	arch/mips/jz4740/

F:	arch/mips/generic/board-ingenic.c

F:	arch/mips/include/asm/mach-ingenic/

F:	arch/mips/ingenic/Kconfig

F:	drivers/clk/ingenic/

F:	drivers/dma/dma-jz4780.c

F:	drivers/gpu/drm/ingenic/

arch/mips/Kbuild.platforms

+0 −2
Original line number Diff line number Diff line
@@ -13,7 +13,6 @@ platform-$(CONFIG_MIPS_COBALT) += cobalt/ 
platform-$(CONFIG_MACH_DECSTATION)	+= dec/

platform-$(CONFIG_MIPS_GENERIC)		+= generic/

platform-$(CONFIG_MACH_JAZZ)		+= jazz/

platform-$(CONFIG_MACH_INGENIC)		+= jz4740/

platform-$(CONFIG_LANTIQ)		+= lantiq/

platform-$(CONFIG_MACH_LOONGSON2EF)	+= loongson2ef/

platform-$(CONFIG_MACH_LOONGSON32)	+= loongson32/
@@ -22,7 +21,6 @@ platform-$(CONFIG_MIPS_MALTA) += mti-malta/ 
platform-$(CONFIG_NLM_COMMON)		+= netlogic/

platform-$(CONFIG_PIC32MZDA)		+= pic32/

platform-$(CONFIG_MACH_PISTACHIO)	+= pistachio/

platform-$(CONFIG_SOC_PNX833X)		+= pnx833x/

platform-$(CONFIG_RALINK)		+= ralink/

platform-$(CONFIG_MIKROTIK_RB532)	+= rb532/

platform-$(CONFIG_SGI_IP22)		+= sgi-ip22/

arch/mips/Kconfig

+111 −47
Original line number Diff line number Diff line
@@ -94,14 +94,34 @@ config MIPS 
config MIPS_FIXUP_BIGPHYS_ADDR

	bool



config MIPS_GENERIC

	bool



config MACH_INGENIC

	bool

	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_LITTLE_ENDIAN

	select SYS_SUPPORTS_ZBOOT

	select DMA_NONCOHERENT

	select IRQ_MIPS_CPU

	select PINCTRL

	select GPIOLIB

	select COMMON_CLK

	select GENERIC_IRQ_CHIP

	select BUILTIN_DTB if MIPS_NO_APPENDED_DTB

	select USE_OF

	select CPU_SUPPORTS_CPUFREQ

	select MIPS_EXTERNAL_TIMER



menu "Machine selection"



choice

	prompt "System type"

	default MIPS_GENERIC

	default MIPS_GENERIC_KERNEL



config MIPS_GENERIC

config MIPS_GENERIC_KERNEL

	bool "Generic board-agnostic MIPS kernel"

	select MIPS_GENERIC

	select BOOT_RAW

	select BUILTIN_DTB

	select CEVT_R4K
@@ -138,6 +158,7 @@ config MIPS_GENERIC 
	select SYS_SUPPORTS_MULTITHREADING

	select SYS_SUPPORTS_RELOCATABLE

	select SYS_SUPPORTS_SMARTMIPS

	select SYS_SUPPORTS_ZBOOT

	select UHI_BOOT

	select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN

	select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
@@ -390,20 +411,11 @@ config MACH_JAZZ 
	  Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and

	  Olivetti M700-10 workstations.



config MACH_INGENIC

config MACH_INGENIC_SOC

	bool "Ingenic SoC based machines"

	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_LITTLE_ENDIAN

	select MIPS_GENERIC

	select MACH_INGENIC

	select SYS_SUPPORTS_ZBOOT_UART16550

	select CPU_SUPPORTS_HUGEPAGES

	select DMA_NONCOHERENT

	select IRQ_MIPS_CPU

	select PINCTRL

	select GPIOLIB

	select COMMON_CLK

	select GENERIC_IRQ_CHIP

	select BUILTIN_DTB if MIPS_NO_APPENDED_DTB

	select USE_OF



config LANTIQ

	bool "Lantiq based platforms"
@@ -476,6 +488,7 @@ config MACH_LOONGSON64 
	select SYS_SUPPORTS_ZBOOT

	select ZONE_DMA32

	select NUMA

	select SMP

	select COMMON_CLK

	select USE_OF

	select BUILTIN_DTB
@@ -569,6 +582,7 @@ config MIPS_MALTA 
	select SYS_SUPPORTS_VPE_LOADER

	select SYS_SUPPORTS_ZBOOT

	select USE_OF

	select WAR_ICACHE_REFILLS

	select ZONE_DMA32 if 64BIT

	help

	  This enables support for the MIPS Technologies Malta evaluation
@@ -590,19 +604,6 @@ config MACH_VR41XX 
	select SYS_SUPPORTS_MIPS16

	select GPIOLIB



config NXP_STB220

	bool "NXP STB220 board"

	select SOC_PNX833X

	help

	  Support for NXP Semiconductors STB220 Development Board.



config NXP_STB225

	bool "NXP 225 board"

	select SOC_PNX833X

	select SOC_PNX8335

	help

	  Support for NXP Semiconductors STB225 Development Board.



config RALINK

	bool "Ralink based machines"

	select CEVT_R4K
@@ -616,6 +617,7 @@ config RALINK 
	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_LITTLE_ENDIAN

	select SYS_SUPPORTS_MIPS16

	select SYS_SUPPORTS_ZBOOT

	select SYS_HAS_EARLY_PRINTK

	select CLKDEV_LOOKUP

	select ARCH_HAS_RESET_CONTROLLER
@@ -652,6 +654,9 @@ config SGI_IP22 
	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_64BIT_KERNEL

	select SYS_SUPPORTS_BIG_ENDIAN

	select WAR_R4600_V1_INDEX_ICACHEOP

	select WAR_R4600_V1_HIT_CACHEOP

	select WAR_R4600_V2_HIT_CACHEOP

	select MIPS_L1_CACHE_SHIFT_7

	help

	  This are the SGI Indy, Challenge S and Indigo2, as well as certain
@@ -679,6 +684,7 @@ config SGI_IP27 
	select SYS_SUPPORTS_BIG_ENDIAN

	select SYS_SUPPORTS_NUMA

	select SYS_SUPPORTS_SMP

	select WAR_R10000_LLSC

	select MIPS_L1_CACHE_SHIFT_7

	select NUMA

	help
@@ -714,6 +720,7 @@ config SGI_IP28 
	select SYS_HAS_EARLY_PRINTK

	select SYS_SUPPORTS_64BIT_KERNEL

	select SYS_SUPPORTS_BIG_ENDIAN

	select WAR_R10000_LLSC

	select MIPS_L1_CACHE_SHIFT_7

	help

	  This is the SGI Indigo2 with R10000 processor.  To compile a Linux
@@ -740,6 +747,7 @@ config SGI_IP30 
	select SYS_SUPPORTS_64BIT_KERNEL

	select SYS_SUPPORTS_BIG_ENDIAN

	select SYS_SUPPORTS_SMP

	select WAR_R10000_LLSC

	select MIPS_L1_CACHE_SHIFT_7

	select ARC_MEMORY

	help
@@ -767,6 +775,7 @@ config SGI_IP32 
	select SYS_HAS_CPU_NEVADA

	select SYS_SUPPORTS_64BIT_KERNEL

	select SYS_SUPPORTS_BIG_ENDIAN

	select WAR_ICACHE_REFILLS

	help

	  If you want this kernel to run on SGI O2 workstation, say Y here.
@@ -890,6 +899,7 @@ config SNI_RM 
	select SYS_SUPPORTS_BIG_ENDIAN

	select SYS_SUPPORTS_HIGHMEM

	select SYS_SUPPORTS_LITTLE_ENDIAN

	select WAR_R4600_V2_HIT_CACHEOP

	help

	  The SNI RM200/300/400 are MIPS-based machines manufactured by

	  Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
@@ -901,6 +911,7 @@ config MACH_TX39XX 


config MACH_TX49XX

	bool "Toshiba TX49 series based machines"

	select WAR_TX49XX_ICACHE_INDEX_INV



config MIKROTIK_RB532

	bool "Mikrotik RB532 boards"
@@ -1026,8 +1037,8 @@ source "arch/mips/bcm47xx/Kconfig" 
source "arch/mips/bcm63xx/Kconfig"

source "arch/mips/bmips/Kconfig"

source "arch/mips/generic/Kconfig"

source "arch/mips/ingenic/Kconfig"

source "arch/mips/jazz/Kconfig"

source "arch/mips/jz4740/Kconfig"

source "arch/mips/lantiq/Kconfig"

source "arch/mips/pic32/Kconfig"

source "arch/mips/pistachio/Kconfig"
@@ -1267,23 +1278,6 @@ config PCI_XTALK_BRIDGE 
config NO_EXCEPT_FILL

	bool



config SOC_PNX833X

	bool

	select CEVT_R4K

	select CSRC_R4K

	select IRQ_MIPS_CPU

	select DMA_NONCOHERENT

	select SYS_HAS_CPU_MIPS32_R2

	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_LITTLE_ENDIAN

	select SYS_SUPPORTS_BIG_ENDIAN

	select SYS_SUPPORTS_MIPS16

	select CPU_MIPSR2_IRQ_VI



config SOC_PNX8335

	bool

	select SOC_PNX833X



config MIPS_SPRAM

	bool
@@ -1620,7 +1614,6 @@ config CPU_P5600 
	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_SUPPORTS_HIGHMEM

	select CPU_SUPPORTS_MSA

	select CPU_SUPPORTS_UNCACHED_ACCELERATED

	select CPU_SUPPORTS_CPUFREQ

	select CPU_MIPSR2_IRQ_VI

	select CPU_MIPSR2_IRQ_EI
@@ -1891,6 +1884,7 @@ config SYS_SUPPORTS_ZBOOT 
	select HAVE_KERNEL_LZMA

	select HAVE_KERNEL_LZO

	select HAVE_KERNEL_XZ

	select HAVE_KERNEL_ZSTD



config SYS_SUPPORTS_ZBOOT_UART16550

	bool
@@ -2272,7 +2266,7 @@ config FORCE_MAX_ZONEORDER 
	default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB

	range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB

	default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB

	range 11 64

	range 0 64

	default "11"

	help

	  The kernel memory allocator divides physically contiguous memory
@@ -2638,6 +2632,76 @@ config MIPS_ASID_BITS_VARIABLE 
config MIPS_CRC_SUPPORT

	bool



# R4600 erratum.  Due to the lack of errata information the exact

# technical details aren't known.  I've experimentally found that disabling

# interrupts during indexed I-cache flushes seems to be sufficient to deal

# with the issue.

config WAR_R4600_V1_INDEX_ICACHEOP

	bool



# Pleasures of the R4600 V1.x.  Cite from the IDT R4600 V1.7 errata:

#

#  18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,

#      Hit_Invalidate_D and Create_Dirty_Excl_D should only be

#      executed if there is no other dcache activity. If the dcache is

#      accessed for another instruction immeidately preceding when these

#      cache instructions are executing, it is possible that the dcache

#      tag match outputs used by these cache instructions will be

#      incorrect. These cache instructions should be preceded by at least

#      four instructions that are not any kind of load or store

#      instruction.

#

#      This is not allowed:    lw

#                              nop

#                              nop

#                              nop

#                              cache       Hit_Writeback_Invalidate_D

#

#      This is allowed:        lw

#                              nop

#                              nop

#                              nop

#                              nop

#                              cache       Hit_Writeback_Invalidate_D

config WAR_R4600_V1_HIT_CACHEOP

	bool



# Writeback and invalidate the primary cache dcache before DMA.

#

# R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,

# Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only

# operate correctly if the internal data cache refill buffer is empty.  These

# CACHE instructions should be separated from any potential data cache miss

# by a load instruction to an uncached address to empty the response buffer."

# (Revision 2.0 device errata from IDT available on https://www.idt.com/

# in .pdf format.)

config WAR_R4600_V2_HIT_CACHEOP

	bool



# From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for

# the line which this instruction itself exists, the following

# operation is not guaranteed."

#

# Workaround: do two phase flushing for Index_Invalidate_I

config WAR_TX49XX_ICACHE_INDEX_INV

	bool



# The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra

# opposes it being called that) where invalid instructions in the same

# I-cache line worth of instructions being fetched may case spurious

# exceptions.

config WAR_ICACHE_REFILLS

	bool



# On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that

# may cause ll / sc and lld / scd sequences to execute non-atomically.

config WAR_R10000_LLSC

	bool



# 34K core erratum: "Problems Executing the TLBR Instruction"

config WAR_MIPS34K_MISSED_ITLB

	bool



#

# - Highmem only makes sense for the 32-bit kernel.

# - The current highmem code will only work properly on physically indexed

arch/mips/alchemy/Kconfig

+0 −11
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

# au1000-style gpio and interrupt controllers

config ALCHEMY_GPIOINT_AU1000

	bool



# au1300-style GPIO/INT controller

config ALCHEMY_GPIOINT_AU1300

	bool



choice

	prompt "Machine type"

	depends on MIPS_ALCHEMY
@@ -15,7 +7,6 @@ choice 
config MIPS_MTX1

	bool "4G Systems MTX-1 board"

	select HAVE_PCI

	select ALCHEMY_GPIOINT_AU1000

	select SYS_SUPPORTS_LITTLE_ENDIAN

	select SYS_HAS_EARLY_PRINTK
@@ -33,13 +24,11 @@ config MIPS_DB1XXX 


config MIPS_XXS1500

	bool "MyCable XXS1500 board"

	select ALCHEMY_GPIOINT_AU1000

	select SYS_SUPPORTS_LITTLE_ENDIAN

	select SYS_HAS_EARLY_PRINTK



config MIPS_GPR

	bool "Trapeze ITS GPR board"

	select ALCHEMY_GPIOINT_AU1000

	select HAVE_PCI

	select SYS_SUPPORTS_LITTLE_ENDIAN

	select SYS_HAS_EARLY_PRINTK

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