Commit 098c7938 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'x86_urgent_for_5.8_rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 fixes from Borislav Petkov:

 - AMD Memory bandwidth counter width fix, by Babu Moger.

 - Use the proper length type in the 32-bit truncate() syscall variant,
   by Jiri Slaby.

 - Reinit IA32_FEAT_CTL during wakeup to fix the case where after
   resume, VMXON would #GP due to VMX not being properly enabled, by
   Sean Christopherson.

 - Fix a static checker warning in the resctrl code, by Dan Carpenter.

 - Add a CR4 pinning mask for bits which cannot change after boot, by
   Kees Cook.

 - Align the start of the loop of __clear_user() to 16 bytes, to improve
   performance on AMD zen1 and zen2 microarchitectures, by Matt Fleming.

* tag 'x86_urgent_for_5.8_rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/asm/64: Align start of __clear_user() loop to 16-bytes
  x86/cpu: Use pinning mask for CR4 bits needing to be 0
  x86/resctrl: Fix a NULL vs IS_ERR() static checker warning in rdt_cdp_peer_get()
  x86/cpu: Reinitialize IA32_FEAT_CTL MSR on BSP during wakeup
  syscalls: Fix offset type of ksys_ftruncate()
  x86/resctrl: Fix memory bandwidth counter width for AMD
parents c141b30e bb5570ad

arch/x86/include/asm/cpu.h

+5 −0
Original line number Diff line number Diff line
@@ -58,4 +58,9 @@ static inline bool handle_guest_split_lock(unsigned long ip) 
	return false;

}

#endif

#ifdef CONFIG_IA32_FEAT_CTL

void init_ia32_feat_ctl(struct cpuinfo_x86 *c);

#else

static inline void init_ia32_feat_ctl(struct cpuinfo_x86 *c) {}

#endif

#endif /* _ASM_X86_CPU_H */

arch/x86/kernel/cpu/centaur.c

+1 −0
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 
#include <linux/sched.h>

#include <linux/sched/clock.h>



#include <asm/cpu.h>

#include <asm/cpufeature.h>

#include <asm/e820/api.h>

#include <asm/mtrr.h>

arch/x86/kernel/cpu/common.c

+12 −12
Original line number Diff line number Diff line
@@ -347,6 +347,9 @@ out: 
	cr4_clear_bits(X86_CR4_UMIP);

}



/* These bits should not change their value after CPU init is finished. */

static const unsigned long cr4_pinned_mask =

	X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP | X86_CR4_FSGSBASE;

static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning);

static unsigned long cr4_pinned_bits __ro_after_init;
@@ -371,20 +374,20 @@ EXPORT_SYMBOL(native_write_cr0); 


void native_write_cr4(unsigned long val)

{

	unsigned long bits_missing = 0;

	unsigned long bits_changed = 0;



set_register:

	asm volatile("mov %0,%%cr4": "+r" (val), "+m" (cr4_pinned_bits));



	if (static_branch_likely(&cr_pinning)) {

		if (unlikely((val & cr4_pinned_bits) != cr4_pinned_bits)) {

			bits_missing = ~val & cr4_pinned_bits;

			val |= bits_missing;

		if (unlikely((val & cr4_pinned_mask) != cr4_pinned_bits)) {

			bits_changed = (val & cr4_pinned_mask) ^ cr4_pinned_bits;

			val = (val & ~cr4_pinned_mask) | cr4_pinned_bits;

			goto set_register;

		}

		/* Warn after we've set the missing bits. */

		WARN_ONCE(bits_missing, "CR4 bits went missing: %lx!?\n",

			  bits_missing);

		/* Warn after we've corrected the changed bits. */

		WARN_ONCE(bits_changed, "pinned CR4 bits changed: 0x%lx!?\n",

			  bits_changed);

	}

}

#if IS_MODULE(CONFIG_LKDTM)
@@ -419,7 +422,7 @@ void cr4_init(void) 
	if (boot_cpu_has(X86_FEATURE_PCID))

		cr4 |= X86_CR4_PCIDE;

	if (static_branch_likely(&cr_pinning))

		cr4 |= cr4_pinned_bits;

		cr4 = (cr4 & ~cr4_pinned_mask) | cr4_pinned_bits;



	__write_cr4(cr4);
@@ -434,10 +437,7 @@ void cr4_init(void) 
 */

static void __init setup_cr_pinning(void)

{

	unsigned long mask;



	mask = (X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP);

	cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & mask;

	cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & cr4_pinned_mask;

	static_key_enable(&cr_pinning.key);

}

arch/x86/kernel/cpu/cpu.h

+0 −4
Original line number Diff line number Diff line
@@ -81,8 +81,4 @@ extern void update_srbds_msr(void); 


extern u64 x86_read_arch_cap_msr(void);



#ifdef CONFIG_IA32_FEAT_CTL

void init_ia32_feat_ctl(struct cpuinfo_x86 *c);

#endif



#endif /* ARCH_X86_CPU_H */

arch/x86/kernel/cpu/resctrl/core.c

+4 −4
Original line number Diff line number Diff line
@@ -981,10 +981,10 @@ void resctrl_cpu_detect(struct cpuinfo_x86 *c) 


		c->x86_cache_max_rmid  = ecx;

		c->x86_cache_occ_scale = ebx;

		if (c->x86_vendor == X86_VENDOR_INTEL)

		c->x86_cache_mbm_width_offset = eax & 0xff;

		else

			c->x86_cache_mbm_width_offset = -1;



		if (c->x86_vendor == X86_VENDOR_AMD && !c->x86_cache_mbm_width_offset)

			c->x86_cache_mbm_width_offset = MBM_CNTR_WIDTH_OFFSET_AMD;

	}

}

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