Commit 09407579 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Store the default sseu setup on the engine



As we push for better compartmentalisation, it is more convenient to
copy the default sseu configuration from the engine into the derived
logical context, than it is to dig it out from i915->runtime_info.

v2: Use intel_sseu_from_device_info() to describe the converter

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190424095134.30249-1-chris@chris-wilson.co.uk
parent 51eb1a1d
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+1 −0
Original line number Diff line number Diff line
@@ -95,6 +95,7 @@ i915-y += \
	  intel_lrc.o \
	  intel_mocs.o \
	  intel_ringbuffer.o \
	  intel_sseu.o \
	  intel_uncore.o \
	  intel_wopcm.o

+1 −0
Original line number Diff line number Diff line
@@ -33,6 +33,7 @@ header_test := \
	intel_psr.h \
	intel_sdvo.h \
	intel_sprite.h \
	intel_sseu.h \
	intel_tv.h \
	intel_workarounds_types.h

+0 −14
Original line number Diff line number Diff line
@@ -3390,20 +3390,6 @@ mkwrite_device_info(struct drm_i915_private *dev_priv)
	return (struct intel_device_info *)INTEL_INFO(dev_priv);
}

static inline struct intel_sseu
intel_device_default_sseu(struct drm_i915_private *i915)
{
	const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
	struct intel_sseu value = {
		.slice_mask = sseu->slice_mask,
		.subslice_mask = sseu->subslice_mask[0],
		.min_eus_per_subslice = sseu->max_eus_per_subslice,
		.max_eus_per_subslice = sseu->max_eus_per_subslice,
	};

	return value;
}

/* modesetting */
extern void intel_modeset_init_hw(struct drm_device *dev);
extern int intel_modeset_init(struct drm_device *dev);
+1 −1
Original line number Diff line number Diff line
@@ -1156,7 +1156,7 @@ static int gen8_emit_rpcs_config(struct i915_request *rq,
	*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
	*cs++ = lower_32_bits(offset);
	*cs++ = upper_32_bits(offset);
	*cs++ = gen8_make_rpcs(rq->i915, &sseu);
	*cs++ = intel_sseu_make_rpcs(rq->i915, &sseu);

	intel_ring_advance(rq, cs);

+1 −1
Original line number Diff line number Diff line
@@ -1679,7 +1679,7 @@ gen8_update_reg_state_unlocked(struct intel_context *ce,

	CTX_REG(reg_state,
		CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
		gen8_make_rpcs(i915, &ce->sseu));
		intel_sseu_make_rpcs(i915, &ce->sseu));
}

/*
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