clk: meson: axg: add hifi pll clock (093c3fac) · Commits · 戴 / test

drivers/clk/meson/axg.c

+55 −0

Original line number	Original line	Diff line number	Diff line
	@@ -245,6 +245,59 @@ static struct clk_regmap axg_gp0_pll = {
	},		},
	};		};

			const struct reg_sequence axg_hifi_init_regs[] = {
			{ .reg = HHI_HIFI_PLL_CNTL1, .def = 0xc084b000 },
			{ .reg = HHI_HIFI_PLL_CNTL2, .def = 0xb75020be },
			{ .reg = HHI_HIFI_PLL_CNTL3, .def = 0x0a6a3a88 },
			{ .reg = HHI_HIFI_PLL_CNTL4, .def = 0xc000004d },
			{ .reg = HHI_HIFI_PLL_CNTL5, .def = 0x00058000 },
			{ .reg = HHI_HIFI_PLL_CNTL, .def = 0x40010250 },
			};

			static struct clk_regmap axg_hifi_pll = {
			.data = &(struct meson_clk_pll_data){
			.m = {
			.reg_off = HHI_HIFI_PLL_CNTL,
			.shift = 0,
			.width = 9,
			},
			.n = {
			.reg_off = HHI_HIFI_PLL_CNTL,
			.shift = 9,
			.width = 5,
			},
			.od = {
			.reg_off = HHI_HIFI_PLL_CNTL,
			.shift = 16,
			.width = 2,
			},
			.frac = {
			.reg_off = HHI_HIFI_PLL_CNTL5,
			.shift = 0,
			.width = 13,
			},
			.l = {
			.reg_off = HHI_HIFI_PLL_CNTL,
			.shift = 31,
			.width = 1,
			},
			.rst = {
			.reg_off = HHI_HIFI_PLL_CNTL,
			.shift = 29,
			.width = 1,
			},
			.table = axg_gp0_pll_rate_table,
			.init_regs = axg_hifi_init_regs,
			.init_count = ARRAY_SIZE(axg_hifi_init_regs),
			.flags = CLK_MESON_PLL_ROUND_CLOSEST,
			},
			.hw.init = &(struct clk_init_data){
			.name = "hifi_pll",
			.ops = &meson_clk_pll_ops,
			.parent_names = (const char *[]){ "xtal" },
			.num_parents = 1,
			},
			};

	static struct clk_fixed_factor axg_fclk_div2 = {		static struct clk_fixed_factor axg_fclk_div2 = {
	.mult = 1,		.mult = 1,
	@@ -767,6 +820,7 @@ static struct clk_hw_onecell_data axg_hw_onecell_data = {
	[CLKID_MPLL1_DIV] = &axg_mpll1_div.hw,		[CLKID_MPLL1_DIV] = &axg_mpll1_div.hw,
	[CLKID_MPLL2_DIV] = &axg_mpll2_div.hw,		[CLKID_MPLL2_DIV] = &axg_mpll2_div.hw,
	[CLKID_MPLL3_DIV] = &axg_mpll3_div.hw,		[CLKID_MPLL3_DIV] = &axg_mpll3_div.hw,
			[CLKID_HIFI_PLL] = &axg_hifi_pll.hw,
	[NR_CLKS] = NULL,		[NR_CLKS] = NULL,
	},		},
	.num = NR_CLKS,		.num = NR_CLKS,
	@@ -838,6 +892,7 @@ static struct clk_regmap *const axg_clk_regmaps[] = {
	&axg_fixed_pll,		&axg_fixed_pll,
	&axg_sys_pll,		&axg_sys_pll,
	&axg_gp0_pll,		&axg_gp0_pll,
			&axg_hifi_pll,
	};		};

	static const struct of_device_id clkc_match_table[] = {		static const struct of_device_id clkc_match_table[] = {

drivers/clk/meson/axg.h

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -122,7 +122,7 @@
	#define CLKID_MPLL2_DIV 67		#define CLKID_MPLL2_DIV 67
	#define CLKID_MPLL3_DIV 68		#define CLKID_MPLL3_DIV 68

	#define NR_CLKS 69		#define NR_CLKS 70

	/* include the CLKIDs that have been made part of the DT binding */		/* include the CLKIDs that have been made part of the DT binding */
	#include <dt-bindings/clock/axg-clkc.h>		#include <dt-bindings/clock/axg-clkc.h>

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