ARM: GIC: Make MULTI_IRQ_HANDLER mandatory

	select ARM_TIMER_SP804

	select GPIO_PL061 if GPIOLIB

	select NEED_MACH_MEMORY_H

	select MULTI_IRQ_HANDLER

	help

	  This enables support for ARM Ltd RealView boards.

	select ICST

	select PLAT_VERSATILE

	select PLAT_VERSATILE_CLCD

	select MULTI_IRQ_HANDLER

	help

	  This enables support for the ARM Ltd Versatile Express boards.

	select GENERIC_CLOCKEVENTS

	select HAVE_ARM_SCU

	select USE_OF

	select MULTI_IRQ_HANDLER

	help

	  Support for the Calxeda Highbank SoC based boards.

	select ARM_GIC

	select MIGHT_HAVE_PCI

	select PCI_DOMAINS if PCI

	select MULTI_IRQ_HANDLER

	help

	  Support for Cavium Networks CNS3XXX platform.

	select HAVE_S3C2410_I2C if I2C

	select HAVE_S3C2410_WATCHDOG if WATCHDOG

	select NEED_MACH_MEMORY_H

	select MULTI_IRQ_HANDLER

	help

	  Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)

	select ARM_AMBA

	select ICST

	select USE_OF

	select MULTI_IRQ_HANDLER

	help

	  Support for Xilinx Zynq ARM Cortex A9 Platform

endchoice

config ARM_GIC

	select IRQ_DOMAIN

	select MULTI_IRQ_HANDLER

	bool

config GIC_NON_BANKED

static DEFINE_RAW_SPINLOCK(irq_controller_lock);

/* Address of GIC 0 CPU interface */

void __iomem *gic_cpu_base_addr __read_mostly;

/*

 * Supported arch specific GIC irq extension.

 * Default make them NULL.

	 * For secondary GICs, skip over PPIs, too.

	 */

	if (gic_nr == 0) {

		gic_cpu_base_addr = cpu_base;

		domain->hwirq_base = 16;

		if (irq_start > 0)

			irq_start = (irq_start & ~31) + 16;

/*

 * arch/arm/include/asm/hardware/entry-macro-gic.S

 *

 * Low-level IRQ helper macros for GIC

 *

 * This file is licensed under  the terms of the GNU General Public

 * License version 2. This program is licensed "as is" without any

 * warranty of any kind, whether express or implied.

 */

#include <asm/hardware/gic.h>

#ifndef HAVE_GET_IRQNR_PREAMBLE

	.macro	get_irqnr_preamble, base, tmp

	ldr	\base, =gic_cpu_base_addr

	ldr	\base, [\base]

	.endm

#endif

/*

 * The interrupt numbering scheme is defined in the

 * interrupt controller spec.  To wit:

 *

 * Interrupts 0-15 are IPI

 * 16-31 are local.  We allow 30 to be used for the watchdog.

 * 32-1020 are global

 * 1021-1022 are reserved

 * 1023 is "spurious" (no interrupt)

 *

 * A simple read from the controller will tell us the number of the highest

 * priority enabled interrupt.  We then just need to check whether it is in the

 * valid range for an IRQ (30-1020 inclusive).

 */

	.macro  get_irqnr_and_base, irqnr, irqstat, base, tmp

	ldr     \irqstat, [\base, #GIC_CPU_INTACK]

	/* bits 12-10 = src CPU, 9-0 = int # */

	ldr	\tmp, =1021

	bic     \irqnr, \irqstat, #0x1c00

	cmp     \irqnr, #15

	cmpcc	\irqnr, \irqnr

	cmpne	\irqnr, \tmp

	cmpcs	\irqnr, \irqnr

	.endm

/* We assume that irqstat (the raw value of the IRQ acknowledge

 * register) is preserved from the macro above.

 * If there is an IPI, we immediately signal end of interrupt on the

 * controller, since this requires the original irqstat value which

 * we won't easily be able to recreate later.

 */

	.macro test_for_ipi, irqnr, irqstat, base, tmp

	bic	\irqnr, \irqstat, #0x1c00

	cmp	\irqnr, #16

	strcc	\irqstat, [\base, #GIC_CPU_EOI]

	cmpcs	\irqnr, \irqnr

	.endm

#include <linux/irqdomain.h>

struct device_node;

extern void __iomem *gic_cpu_base_addr;

extern struct irq_chip gic_arch_extn;

void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,