Commit 08ceab9d authored by Takashi Iwai's avatar Takashi Iwai
Browse files

Merge tag 'asoc-v4.2-rc8' of... 

Merge tag 'asoc-v4.2-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-linus

ASoC: Updates for v4.3

Not many updates to the core here, but an awful lot of driver updates
this time round:

 - Factoring out of AC'97 reset code into the core
 - New drivers for Cirrus CS4349, GTM601, InvenSense ICS43432, Realtek
   RT298 and ST STI controllers.
 - Machine drivers for Rockchip systems with MAX98090 and RT5645 and
   RT5650.
 - Initial driver support for Intel Skylake devices.
 - A large number of cleanups for Lars-Peter Clausen and Axel Lin.
parents 22c103cd 91931320

.get_maintainer.ignore

0 → 100644
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Christoph Hellwig <hch@lst.de>

.mailmap

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@@ -17,6 +17,7 @@ Aleksey Gorelov <aleksey_gorelov@phoenix.com> 
Al Viro <viro@ftp.linux.org.uk>

Al Viro <viro@zenIV.linux.org.uk>

Andreas Herrmann <aherrman@de.ibm.com>

Andrey Ryabinin <ryabinin.a.a@gmail.com> <a.ryabinin@samsung.com>

Andrew Morton <akpm@linux-foundation.org>

Andrew Vasquez <andrew.vasquez@qlogic.com>

Andy Adamson <andros@citi.umich.edu>

Documentation/DocBook/alsa-driver-api.tmpl

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@@ -108,7 +108,7 @@ 
     <sect1><title>ASoC Core API</title>

!Iinclude/sound/soc.h

!Esound/soc/soc-core.c

!Esound/soc/soc-cache.c

<!-- !Esound/soc/soc-cache.c no docbook comments here -->

!Esound/soc/soc-devres.c

!Esound/soc/soc-io.c

!Esound/soc/soc-pcm.c

Documentation/devicetree/bindings/arm/cpus.txt

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@@ -199,6 +199,7 @@ nodes to be present and contain the properties described below. 
			    "qcom,kpss-acc-v1"

			    "qcom,kpss-acc-v2"

			    "rockchip,rk3066-smp"

			    "ste,dbx500-smp"



	- cpu-release-addr

		Usage: required for systems that have an "enable-method"

Documentation/devicetree/bindings/phy/ti-phy.txt

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@@ -82,6 +82,9 @@ Optional properties: 
 - id: If there are multiple instance of the same type, in order to

   differentiate between each instance "id" can be used (e.g., multi-lane PCIe

   PHY). If "id" is not provided, it is set to default value of '1'.

 - syscon-pllreset: Handle to system control region that contains the

   CTRL_CORE_SMA_SW_0 register and register offset to the CTRL_CORE_SMA_SW_0

   register that contains the SATA_PLL_SOFT_RESET bit. Only valid for sata_phy.



This is usually a subnode of ocp2scp to which it is connected.
@@ -100,3 +103,16 @@ usb3phy@4a084400 { 
			"sysclk",

			"refclk";

};



sata_phy: phy@4A096000 {

	compatible = "ti,phy-pipe3-sata";

	reg = <0x4A096000 0x80>, /* phy_rx */

	      <0x4A096400 0x64>, /* phy_tx */

	      <0x4A096800 0x40>; /* pll_ctrl */

	reg-names = "phy_rx", "phy_tx", "pll_ctrl";

	ctrl-module = <&omap_control_sata>;

	clocks = <&sys_clkin1>, <&sata_ref_clk>;

	clock-names = "sysclk", "refclk";

	syscon-pllreset = <&scm_conf 0x3fc>;

	#phy-cells = <0>;

};

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