Commit 08a5f1ac authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'arm-soc/for-4.18/soc' of https://github.com/Broadcom/stblinux into next/soc 

This pull request contains Broadcom ARM-based machine/platform files
changes for 4.18, please pull the following:

- Doug updates arch/arm/include/asm/cpuinfo.h such that this header file
can be used by both C and assembly code. This particular change will
also be included in a Sunxi pull request to support A83T SMP support.

- Doug also updates our DEBUG_LL routine to support newer chips such as
7278 which have a version 7 memory map which moves the registers from
physical address 0xf000_0000 down to 0x0800_0000. This requires us to
look up the processor MIDR and determine the base address from the
PERIPHBASE register.

- Florian updates the Brahma-B15 read-ahead cache implementation such
that it works on the Brahma-B53 CPUs, which also have an identical
read-ahead cache implementation, with a different set of offsets. He
also provides the Brahma-B15 MIDR definition such that it can be used by
other pieces of code in the future.

* tag 'arm-soc/for-4.18/soc' of https://github.com/Broadcom/stblinux

:
  ARM: brcmstb: Add support for the V7 memory map
  ARM: add Broadcom Brahma-B15 main ID definition
  ARM: add Broadcom Brahma-B53 main ID definition
  ARM: Allow this header to be included by assembly files
  ARM: B15: Update to support Brahma-B53

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents e5d9875e 56e4446d

arch/arm/include/asm/cputype.h

+12 −3
Original line number Diff line number Diff line
@@ -2,9 +2,6 @@ 
#ifndef __ASM_ARM_CPUTYPE_H

#define __ASM_ARM_CPUTYPE_H



#include <linux/stringify.h>

#include <linux/kernel.h>



#define CPUID_ID	0

#define CPUID_CACHETYPE	1

#define CPUID_TCM	2
@@ -62,6 +59,7 @@ 
	((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK)



#define ARM_CPU_IMP_ARM			0x41

#define ARM_CPU_IMP_BRCM		0x42

#define ARM_CPU_IMP_DEC			0x44

#define ARM_CPU_IMP_INTEL		0x69
@@ -79,6 +77,10 @@ 
#define ARM_CPU_PART_CORTEX_A15		0x4100c0f0

#define ARM_CPU_PART_MASK		0xff00fff0



/* Broadcom implemented processors */

#define ARM_CPU_PART_BRAHMA_B15		0x420000f0

#define ARM_CPU_PART_BRAHMA_B53		0x42001000



/* DEC implemented cores */

#define ARM_CPU_PART_SA1100		0x4400a110
@@ -98,6 +100,11 @@ 
/* Qualcomm implemented cores */

#define ARM_CPU_PART_SCORPION		0x510002d0



#ifndef __ASSEMBLY__



#include <linux/stringify.h>

#include <linux/kernel.h>



extern unsigned int processor_id;



#ifdef CONFIG_CPU_CP15
@@ -326,4 +333,6 @@ static inline int __attribute_const__ cpuid_feature_extract_field(u32 features, 
#define cpuid_feature_extract(reg, field) \

	cpuid_feature_extract_field(read_cpuid_ext(reg), field)



#endif /* __ASSEMBLY__ */



#endif

arch/arm/include/debug/brcmstb.S

+20 −1
Original line number Diff line number Diff line
@@ -11,20 +11,25 @@ 
 * GNU General Public License for more details.

 */

#include <linux/serial_reg.h>

#include <asm/cputype.h>



/* Physical register offset and virtual register offset */

#define REG_PHYS_BASE		0xf0000000

#define REG_PHYS_BASE_V7	0x08000000

#define REG_VIRT_BASE		0xfc000000

#define REG_PHYS_ADDR(x)	((x) + REG_PHYS_BASE)

#define REG_PHYS_ADDR_V7(x)	((x) + REG_PHYS_BASE_V7)



/* Product id can be read from here */

#define SUN_TOP_CTRL_BASE	REG_PHYS_ADDR(0x404000)

#define SUN_TOP_CTRL_BASE_V7	REG_PHYS_ADDR_V7(0x404000)



#define UARTA_3390		REG_PHYS_ADDR(0x40a900)

#define UARTA_7250		REG_PHYS_ADDR(0x40b400)

#define UARTA_7260		REG_PHYS_ADDR(0x40c000)

#define UARTA_7268		UARTA_7260

#define UARTA_7271		UARTA_7268

#define UARTA_7278		REG_PHYS_ADDR_V7(0x40c000)

#define UARTA_7364		REG_PHYS_ADDR(0x40b000)

#define UARTA_7366		UARTA_7364

#define UARTA_74371		REG_PHYS_ADDR(0x406b00)
@@ -55,8 +60,21 @@ 
		mov	\rv, #0			@ yes; record init is done

		str	\rv, [\tmp]



		/* Check for V7 memory map if B53 */

		mrc	p15, 0, \rv, c0, c0, 0	@ get Main ID register

		ldr	\rp, =ARM_CPU_PART_MASK

		and	\rv, \rv, \rp

		ldr	\rp, =ARM_CPU_PART_BRAHMA_B53	@ check for B53 CPU

		cmp	\rv, \rp

		bne	10f



		/* if PERIPHBASE doesn't overlap REG_PHYS_BASE use V7 map */

		mrc	p15, 1, \rv, c15, c3, 0	@ get PERIPHBASE from CBAR

		ands	\rv, \rv, #REG_PHYS_BASE

		ldreq	\rp, =SUN_TOP_CTRL_BASE_V7



		/* Check SUN_TOP_CTRL base */

		ldr	\rp, =SUN_TOP_CTRL_BASE	@ load SUN_TOP_CTRL PA

10:		ldrne	\rp, =SUN_TOP_CTRL_BASE	@ load SUN_TOP_CTRL PA

		ldr	\rv, [\rp, #0]		@ get register contents

ARM_BE8(	rev	\rv, \rv )

		and	\rv, \rv, #0xffffff00	@ strip revision bits [7:0]
@@ -72,6 +90,7 @@ ARM_BE8( rev \rv, \rv ) 
27:		checkuart(\rp, \rv, 0x07437100, 74371)

28:		checkuart(\rp, \rv, 0x74390000, 7439)

29:		checkuart(\rp, \rv, 0x74450000, 7445)

30:		checkuart(\rp, \rv, 0x72780000, 7278)



		/* No valid UART found */

90:		mov	\rp, #0

arch/arm/mm/cache-b15-rac.c

+26 −4
Original line number Diff line number Diff line
@@ -33,7 +33,10 @@ extern void v7_flush_kern_cache_all(void); 
#define  RAC_CPU_SHIFT			(8)

#define  RACCFG_MASK			(0xff)

#define RAC_CONFIG1_REG			(0x7c)

#define RAC_FLUSH_REG			(0x80)

/* Brahma-B15 is a quad-core only design */

#define B15_RAC_FLUSH_REG		(0x80)

/* Brahma-B53 is an octo-core design */

#define B53_RAC_FLUSH_REG		(0x84)

#define  FLUSH_RAC			(1 << 0)



/* Bitmask to enable instruction and data prefetching with a 256-bytes stride */
@@ -52,6 +55,7 @@ static void __iomem *b15_rac_base; 
static DEFINE_SPINLOCK(rac_lock);



static u32 rac_config0_reg;

static u32 rac_flush_offset;



/* Initialization flag to avoid checking for b15_rac_base, and to prevent

 * multi-platform kernels from crashing here as well.
@@ -70,14 +74,14 @@ static inline void __b15_rac_flush(void) 
{

	u32 reg;



	__raw_writel(FLUSH_RAC, b15_rac_base + RAC_FLUSH_REG);

	__raw_writel(FLUSH_RAC, b15_rac_base + rac_flush_offset);

	do {

		/* This dmb() is required to force the Bus Interface Unit

		 * to clean oustanding writes, and forces an idle cycle

		 * to be inserted.

		 */

		dmb();

		reg = __raw_readl(b15_rac_base + RAC_FLUSH_REG);

		reg = __raw_readl(b15_rac_base + rac_flush_offset);

	} while (reg & FLUSH_RAC);

}
@@ -287,7 +291,7 @@ static struct syscore_ops b15_rac_syscore_ops = { 


static int __init b15_rac_init(void)

{

	struct device_node *dn;

	struct device_node *dn, *cpu_dn;

	int ret = 0, cpu;

	u32 reg, en_mask = 0;
@@ -305,6 +309,24 @@ static int __init b15_rac_init(void) 
		goto out;

	}



	cpu_dn = of_get_cpu_node(0, NULL);

	if (!cpu_dn) {

		ret = -ENODEV;

		goto out;

	}



	if (of_device_is_compatible(cpu_dn, "brcm,brahma-b15"))

		rac_flush_offset = B15_RAC_FLUSH_REG;

	else if (of_device_is_compatible(cpu_dn, "brcm,brahma-b53"))

		rac_flush_offset = B53_RAC_FLUSH_REG;

	else {

		pr_err("Unsupported CPU\n");

		of_node_put(cpu_dn);

		ret = -EINVAL;

		goto out;

	}

	of_node_put(cpu_dn);



	ret = register_reboot_notifier(&b15_rac_reboot_nb);

	if (ret) {

		pr_err("failed to register reboot notifier\n");

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