clk: renesas: r8a7792: Fix LB clock divider (0873305e) · Commits · 戴 / test

The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where the LB clock divider depends on the value of the MD18 pin. On R-Car V2H, the LB clock divider is fixed to 24. Hence model the clock as a fixed factor clock instead. Signed-off-by:

Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by:

Simon Horman <horms+renesas@verge.net.au> Reviewed-by:

Fabrizio Castro <fabrizio.castro@bp.renesas.com>

drivers/clk/renesas/r8a7792-cpg-mssr.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -53,7 +53,6 @@ static const struct cpg_core_clk r8a7792_core_clks[] __initconst = {
		DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),

		/* Core Clock Outputs */
		DEF_BASE("lb", R8A7792_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
		DEF_BASE("qspi", R8A7792_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),

		DEF_FIXED("z", R8A7792_CLK_Z, CLK_PLL0, 1, 1),
		@@ -63,6 +62,7 @@ static const struct cpg_core_clk r8a7792_core_clks[] __initconst = {
		DEF_FIXED("hp", R8A7792_CLK_HP, CLK_PLL1, 12, 1),
		DEF_FIXED("i", R8A7792_CLK_I, CLK_PLL1, 3, 1),
		DEF_FIXED("b", R8A7792_CLK_B, CLK_PLL1, 12, 1),
		DEF_FIXED("lb", R8A7792_CLK_LB, CLK_PLL1, 24, 1),
		DEF_FIXED("p", R8A7792_CLK_P, CLK_PLL1, 24, 1),
		DEF_FIXED("cl", R8A7792_CLK_CL, CLK_PLL1, 48, 1),
		DEF_FIXED("m2", R8A7792_CLK_M2, CLK_PLL1, 8, 1),

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