drm/amd/amdgpu: L1 Policy(2/5) - removed GC GRBM violations from gfxhub (08546895) · Commits · 戴 / test

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

+43 −36

Original line number	Diff line number	Diff line
		@@ -75,27 +75,31 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
		WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
		WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);

		if (!amdgpu_sriov_vf(adev) \|\| adev->asic_type <= CHIP_VEGA10) {
		/* Program the system aperture low logical page number. */
		WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
		min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);

		if (adev->asic_type == CHIP_RAVEN && adev->rev_id >= 0x8)
		/*
		* Raven2 has a HW issue that it is unable to use the vram which
		* is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
		* workaround that increase system aperture high address (add 1)
		* to get rid of the VM fault and hardware hang.
		* Raven2 has a HW issue that it is unable to use the
		* vram which is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR.
		* So here is the workaround that increase system
		* aperture high address (add 1) to get rid of the VM
		* fault and hardware hang.
		*/
		WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
		WREG32_SOC15_RLC(GC, 0,
		mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
		max((adev->gmc.fb_end >> 18) + 0x1,
		adev->gmc.agp_end >> 18));
		else
		WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
		WREG32_SOC15_RLC(
		GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
		max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);

		/* Set default page address. */
		value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start
		+ adev->vm_manager.vram_base_offset;
		value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
		adev->vm_manager.vram_base_offset;
		WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
		(u32)(value >> 12));
		WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
		@@ -110,6 +114,7 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
		WREG32_FIELD15(GC, 0, VM_L2_PROTECTION_FAULT_CNTL2,
		ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
		}
		}

		static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
		{
		@@ -280,9 +285,11 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
		gfxhub_v1_0_init_gart_aperture_regs(adev);
		gfxhub_v1_0_init_system_aperture_regs(adev);
		gfxhub_v1_0_init_tlb_regs(adev);
		if (!amdgpu_sriov_vf(adev))
		gfxhub_v1_0_init_cache_regs(adev);

		gfxhub_v1_0_enable_system_domain(adev);
		if (!amdgpu_sriov_vf(adev))
		gfxhub_v1_0_disable_identity_aperture(adev);
		gfxhub_v1_0_setup_vmid_config(adev);
		gfxhub_v1_0_program_invalidation(adev);

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -1307,8 +1307,8 @@ static int gmc_v9_0_hw_init(void *handle)
		else
		value = true;

		gfxhub_v1_0_set_fault_enable_default(adev, value);
		if (!amdgpu_sriov_vf(adev)) {
		gfxhub_v1_0_set_fault_enable_default(adev, value);
		if (adev->asic_type == CHIP_ARCTURUS)
		mmhub_v9_4_set_fault_enable_default(adev, value);
		else

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