arm64: dts: meson-g12a: Add VPU and HDMI related nodes (083feecd) · Commits · 戴 / test

arch/arm64/boot/dts/amlogic/meson-g12a.dtsi

+131 −0

Original line number	Diff line number	Diff line
		@@ -109,6 +109,37 @@
		#size-cells = <2>;
		ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>;

		hdmi_tx: hdmi-tx@0 {
		compatible = "amlogic,meson-g12a-dw-hdmi";
		reg = <0x0 0x0 0x0 0x10000>;
		interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
		resets = <&reset RESET_HDMITX_CAPB3>,
		<&reset RESET_HDMITX_PHY>,
		<&reset RESET_HDMITX>;
		reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
		clocks = <&clkc CLKID_HDMI>,
		<&clkc CLKID_HTX_PCLK>,
		<&clkc CLKID_VPU_INTR>;
		clock-names = "isfr", "iahb", "venci";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";

		/* VPU VENC Input */
		hdmi_tx_venc_port: port@0 {
		reg = <0>;

		hdmi_tx_in: endpoint {
		remote-endpoint = <&hdmi_tx_out>;
		};
		};

		/* TMDS Output */
		hdmi_tx_tmds_port: port@1 {
		reg = <1>;
		};
		};

		periphs: bus@34400 {
		compatible = "simple-bus";
		reg = <0x0 0x34400 0x0 0x400>;
		@@ -138,6 +169,23 @@
		gpio-ranges = <&periphs_pinctrl 0 0 86>;
		};

		hdmitx_ddc_pins: hdmitx_ddc {
		mux {
		groups = "hdmitx_sda",
		"hdmitx_sck";
		function = "hdmitx";
		bias-disable;
		};
		};

		hdmitx_hpd_pins: hdmitx_hpd {
		mux {
		groups = "hdmitx_hpd_in";
		function = "hdmitx";
		bias-disable;
		};
		};

		uart_a_pins: uart-a {
		mux {
		groups = "uart_a_tx",
		@@ -195,6 +243,19 @@
		#phy-cells = <0>;
		};

		dmc: bus@38000 {
		compatible = "simple-bus";
		reg = <0x0 0x38000 0x0 0x400>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>;

		canvas: video-lut@48 {
		compatible = "amlogic,canvas";
		reg = <0x0 0x48 0x0 0x14>;
		};
		};

		usb2_phy1: phy@3a000 {
		compatible = "amlogic,g12a-usb2-phy";
		reg = <0x0 0x3a000 0x0 0x2000>;
		@@ -262,6 +323,50 @@
		clock-names = "xtal", "mpeg-clk";
		};

		pwrc_vpu: power-controller-vpu {
		compatible = "amlogic,meson-g12a-pwrc-vpu";
		#power-domain-cells = <0>;
		amlogic,hhi-sysctrl = <&hhi>;
		resets = <&reset RESET_VIU>,
		<&reset RESET_VENC>,
		<&reset RESET_VCBUS>,
		<&reset RESET_BT656>,
		<&reset RESET_RDMA>,
		<&reset RESET_VENCI>,
		<&reset RESET_VENCP>,
		<&reset RESET_VDAC>,
		<&reset RESET_VDI6>,
		<&reset RESET_VENCL>,
		<&reset RESET_VID_LOCK>;
		clocks = <&clkc CLKID_VPU>,
		<&clkc CLKID_VAPB>;
		clock-names = "vpu", "vapb";
		/*
		* VPU clocking is provided by two identical clock paths
		* VPU_0 and VPU_1 muxed to a single clock by a glitch
		* free mux to safely change frequency while running.
		* Same for VAPB but with a final gate after the glitch free mux.
		*/
		assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
		<&clkc CLKID_VPU_0>,
		<&clkc CLKID_VPU>, /* Glitch free mux */
		<&clkc CLKID_VAPB_0_SEL>,
		<&clkc CLKID_VAPB_0>,
		<&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
		assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
		<0>, /* Do Nothing */
		<&clkc CLKID_VPU_0>,
		<&clkc CLKID_FCLK_DIV4>,
		<0>, /* Do Nothing */
		<&clkc CLKID_VAPB_0>;
		assigned-clock-rates = <0>, /* Do Nothing */
		<666666666>,
		<0>, /* Do Nothing */
		<0>, /* Do Nothing */
		<250000000>,
		<0>; /* Do Nothing */
		};

		ao_pinctrl: pinctrl@14 {
		compatible = "amlogic,meson-g12a-aobus-pinctrl";
		#address-cells = <2>;
		@@ -341,6 +446,32 @@
		};
		};

		vpu: vpu@ff900000 {
		compatible = "amlogic,meson-g12a-vpu";
		reg = <0x0 0xff900000 0x0 0x100000>,
		<0x0 0xff63c000 0x0 0x1000>;
		reg-names = "vpu", "hhi";
		interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
		#address-cells = <1>;
		#size-cells = <0>;
		amlogic,canvas = <&canvas>;
		power-domains = <&pwrc_vpu>;

		/* CVBS VDAC output port */
		cvbs_vdac_port: port@0 {
		reg = <0>;
		};

		/* HDMI-TX output port */
		hdmi_tx_port: port@1 {
		reg = <1>;

		hdmi_tx_out: endpoint {
		remote-endpoint = <&hdmi_tx_in>;
		};
		};
		};

		gic: interrupt-controller@ffc01000 {
		compatible = "arm,gic-400";
		reg = <0x0 0xffc01000 0 0x1000>,

Admin message