Commit 08351fc6 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile 

* git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile: (27 commits)
  arch/tile: support newer binutils assembler shift semantics
  arch/tile: fix deadlock bugs in rwlock implementation
  drivers/edac: provide support for tile architecture
  tile on-chip network driver: sync up with latest fixes
  arch/tile: support 4KB page size as well as 64KB
  arch/tile: add some more VMSPLIT options and use consistent naming
  arch/tile: fix some comments and whitespace
  arch/tile: export some additional module symbols
  arch/tile: enhance existing finv_buffer_remote() routine
  arch/tile: fix two bugs in the backtracer code
  arch/tile: use extended assembly to inline __mb_incoherent()
  arch/tile: use a cleaner technique to enable interrupt for cpu_idle()
  arch/tile: sync up with <arch/sim.h> and <arch/sim_def.h> changes
  arch/tile: fix reversed test of strict_strtol() return value
  arch/tile: avoid a simulator warning during bootup
  arch/tile: export <asm/hardwall.h> to userspace
  arch/tile: warn and retry if an IPI is not accepted by the target cpu
  arch/tile: stop disabling INTCTRL_1 interrupts during hypervisor downcalls
  arch/tile: fix __ndelay etc to work better
  arch/tile: bug fix: exec'ed task thought it was still single-stepping
  ...

Fix up trivial conflict in arch/tile/kernel/vmlinux.lds.S (percpu
alignment vs section naming convention fix)
parents 0df0914d 0dccb048

MAINTAINERS

+1 −0
Original line number Diff line number Diff line
@@ -6127,6 +6127,7 @@ S: Supported 
F:	arch/tile/

F:	drivers/tty/hvc/hvc_tile.c

F:	drivers/net/tile/

F:	drivers/edac/tile_edac.c



TLAN NETWORK DRIVER

M:	Samuel Chessman <chessman@tux.org>

README

+1 −1
Original line number Diff line number Diff line
@@ -24,7 +24,7 @@ ON WHAT HARDWARE DOES IT RUN? 
  today Linux also runs on (at least) the Compaq Alpha AXP, Sun SPARC and

  UltraSPARC, Motorola 68000, PowerPC, PowerPC64, ARM, Hitachi SuperH, Cell,

  IBM S/390, MIPS, HP PA-RISC, Intel IA-64, DEC VAX, AMD x86-64, AXIS CRIS,

  Xtensa, AVR32 and Renesas M32R architectures.

  Xtensa, Tilera TILE, AVR32 and Renesas M32R architectures.



  Linux is easily portable to most general-purpose 32- or 64-bit architectures

  as long as they have a paged memory management unit (PMMU) and a port of the

arch/tile/Kconfig

+20 −19
Original line number Diff line number Diff line 
# For a description of the syntax of this configuration file,

# see Documentation/kbuild/config-language.txt.

# see Documentation/kbuild/kconfig-language.txt.



config TILE

	def_bool y
@@ -11,6 +11,7 @@ config TILE 
	select HAVE_GENERIC_HARDIRQS

	select GENERIC_IRQ_PROBE

	select GENERIC_PENDING_IRQ if SMP

	select GENERIC_HARDIRQS_NO_DEPRECATED



# FIXME: investigate whether we need/want these options.

#	select HAVE_IOREMAP_PROT
@@ -201,12 +202,6 @@ config NODES_SHIFT 
	  By default, 2, i.e. 2^2 == 4 DDR2 controllers.

	  In a system with more controllers, this value should be raised.



# Need 16MB areas to enable hugetlb

# See build-time check in arch/tile/mm/init.c.

config FORCE_MAX_ZONEORDER

	int

	default 9



choice

	depends on !TILEGX

	prompt "Memory split" if EXPERT
@@ -233,8 +228,12 @@ choice 
		bool "3.5G/0.5G user/kernel split"

	config VMSPLIT_3G

		bool "3G/1G user/kernel split"

	config VMSPLIT_3G_OPT

		bool "3G/1G user/kernel split (for full 1G low memory)"

	config VMSPLIT_2_75G

		bool "2.75G/1.25G user/kernel split (for full 1G low memory)"

	config VMSPLIT_2_5G

		bool "2.5G/1.5G user/kernel split"

	config VMSPLIT_2_25G

		bool "2.25G/1.75G user/kernel split"

	config VMSPLIT_2G

		bool "2G/2G user/kernel split"

	config VMSPLIT_1G
@@ -245,7 +244,9 @@ config PAGE_OFFSET 
	hex

	default 0xF0000000 if VMSPLIT_3_75G

	default 0xE0000000 if VMSPLIT_3_5G

	default 0xB0000000 if VMSPLIT_3G_OPT

	default 0xB0000000 if VMSPLIT_2_75G

	default 0xA0000000 if VMSPLIT_2_5G

	default 0x90000000 if VMSPLIT_2_25G

	default 0x80000000 if VMSPLIT_2G

	default 0x40000000 if VMSPLIT_1G

	default 0xC0000000

arch/tile/include/arch/interrupts_32.h

+6 −3
Original line number Diff line number Diff line
@@ -16,10 +16,11 @@ 
#define __ARCH_INTERRUPTS_H__



/** Mask for an interrupt. */

#ifdef __ASSEMBLER__

/* Note: must handle breaking interrupts into high and low words manually. */

#define INT_MASK(intno) (1 << (intno))

#else

#define INT_MASK_LO(intno) (1 << (intno))

#define INT_MASK_HI(intno) (1 << ((intno) - 32))



#ifndef __ASSEMBLER__

#define INT_MASK(intno) (1ULL << (intno))

#endif
@@ -89,6 +90,7 @@ 


#define NUM_INTERRUPTS 49



#ifndef __ASSEMBLER__

#define QUEUED_INTERRUPTS ( \

    INT_MASK(INT_MEM_ERROR) | \

    INT_MASK(INT_DMATLB_MISS) | \
@@ -301,4 +303,5 @@ 
    INT_MASK(INT_DOUBLE_FAULT) | \

    INT_MASK(INT_AUX_PERF_COUNT) | \

    0)

#endif /* !__ASSEMBLER__ */

#endif /* !__ARCH_INTERRUPTS_H__ */

arch/tile/include/arch/sim.h

+36 −12
Original line number Diff line number Diff line
@@ -152,16 +152,33 @@ sim_dump(unsigned int mask) 
/**

 * Print a string to the simulator stdout.

 *

 * @param str The string to be written; a newline is automatically added.

 * @param str The string to be written.

 */

static __inline void

sim_print(const char* str)

{

  for ( ; *str != '\0'; str++)

  {

    __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PUTC |

                 (*str << _SIM_CONTROL_OPERATOR_BITS));

  }

  __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PUTC |

               (SIM_PUTC_FLUSH_BINARY << _SIM_CONTROL_OPERATOR_BITS));

}





/**

 * Print a string to the simulator stdout.

 *

 * @param str The string to be written (a newline is automatically added).

 */

static __inline void

sim_print_string(const char* str)

{

  int i;

  for (i = 0; str[i] != 0; i++)

  for ( ; *str != '\0'; str++)

  {

    __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PUTC |

                 (str[i] << _SIM_CONTROL_OPERATOR_BITS));

                 (*str << _SIM_CONTROL_OPERATOR_BITS));

  }

  __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PUTC |

               (SIM_PUTC_FLUSH_STRING << _SIM_CONTROL_OPERATOR_BITS));
@@ -203,7 +220,7 @@ sim_command(const char* str) 
 * we are passing to the simulator are actually valid in the registers

 * (i.e. returned from memory) prior to the SIM_CONTROL spr.

 */

static __inline int _sim_syscall0(int val)

static __inline long _sim_syscall0(int val)

{

  long result;

  __asm__ __volatile__ ("mtspr SIM_CONTROL, r0"
@@ -211,7 +228,7 @@ static __inline int _sim_syscall0(int val) 
  return result;

}



static __inline int _sim_syscall1(int val, long arg1)

static __inline long _sim_syscall1(int val, long arg1)

{

  long result;

  __asm__ __volatile__ ("{ and zero, r1, r1; mtspr SIM_CONTROL, r0 }"
@@ -219,7 +236,7 @@ static __inline int _sim_syscall1(int val, long arg1) 
  return result;

}



static __inline int _sim_syscall2(int val, long arg1, long arg2)

static __inline long _sim_syscall2(int val, long arg1, long arg2)

{

  long result;

  __asm__ __volatile__ ("{ and zero, r1, r2; mtspr SIM_CONTROL, r0 }"
@@ -233,7 +250,7 @@ static __inline int _sim_syscall2(int val, long arg1, long arg2) 
   the register values for arguments 3 and up may still be in flight

   to the core from a stack frame reload. */



static __inline int _sim_syscall3(int val, long arg1, long arg2, long arg3)

static __inline long _sim_syscall3(int val, long arg1, long arg2, long arg3)

{

  long result;

  __asm__ __volatile__ ("{ and zero, r3, r3 };"
@@ -244,7 +261,7 @@ static __inline int _sim_syscall3(int val, long arg1, long arg2, long arg3) 
  return result;

}



static __inline int _sim_syscall4(int val, long arg1, long arg2, long arg3,

static __inline long _sim_syscall4(int val, long arg1, long arg2, long arg3,

                                  long arg4)

{

  long result;
@@ -256,7 +273,7 @@ static __inline int _sim_syscall4(int val, long arg1, long arg2, long arg3, 
  return result;

}



static __inline int _sim_syscall5(int val, long arg1, long arg2, long arg3,

static __inline long _sim_syscall5(int val, long arg1, long arg2, long arg3,

                                  long arg4, long arg5)

{

  long result;
@@ -268,7 +285,6 @@ static __inline int _sim_syscall5(int val, long arg1, long arg2, long arg3, 
  return result;

}





/**

 * Make a special syscall to the simulator itself, if running under

 * simulation. This is used as the implementation of other functions
@@ -281,7 +297,8 @@ static __inline int _sim_syscall5(int val, long arg1, long arg2, long arg3, 
 */

#define _sim_syscall(syscall_num, nr, args...) \

  _sim_syscall##nr( \

    ((syscall_num) << _SIM_CONTROL_OPERATOR_BITS) | SIM_CONTROL_SYSCALL, args)

    ((syscall_num) << _SIM_CONTROL_OPERATOR_BITS) | SIM_CONTROL_SYSCALL, \

    ##args)





/* Values for the "access_mask" parameters below. */
@@ -365,6 +382,13 @@ sim_validate_lines_evicted(unsigned long long pa, unsigned long length) 
}





/* Return the current CPU speed in cycles per second. */

static __inline long

sim_query_cpu_speed(void)

{

  return _sim_syscall(SIM_SYSCALL_QUERY_CPU_SPEED, 0);

}



#endif /* !__DOXYGEN__ */

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