Commit 0813c405 authored May 01, 2020 by Kan Liang Committed by Peter Zijlstra May 19, 2020

perf/x86/intel: Add more available bits for OFFCORE_RESPONSE of Intel Tremont



The mask in the extra_regs for Intel Tremont need to be extended to
allow more defined bits.

"Outstanding Requests" (bit 63) is only available on MSR_OFFCORE_RSP0;

Fixes: 6daeb873 ("perf/x86/intel: Add Tremont core PMU support")
Reported-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/20200501125442.7030-1-kan.liang@linux.intel.com

parent f649fc2e

arch/x86/events/intel/core.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -1892,8 +1892,8 @@ static __initconst const u64 tnt_hw_cache_extra_regs

		static struct extra_reg intel_tnt_extra_regs[] __read_mostly = {
		/* must define OFFCORE_RSP_X first, see intel_fixup_er() */
		INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffffff9fffull, RSP_0),
		INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xffffff9fffull, RSP_1),
		INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0),
		INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff0ffffff9fffull, RSP_1),
		EVENT_EXTRA_END
		};

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