Commit 080fe0b7 authored Aug 24, 2016 by Matt Fleming Committed by Ingo Molnar Sep 16, 2016

perf/x86/amd: Make HW_CACHE_REFERENCES and HW_CACHE_MISSES measure L2



While the Intel PMU monitors the LLC when perf enables the
HW_CACHE_REFERENCES and HW_CACHE_MISSES events, these events monitor
L1 instruction cache fetches (0x0080) and instruction cache misses
(0x0081) on the AMD PMU.

This is extremely confusing when monitoring the same workload across
Intel and AMD machines, since parameters like,

  $ perf stat -e cache-references,cache-misses

measure completely different things.

Instead, make the AMD PMU measure instruction/data cache and TLB fill
requests to the L2 and instruction/data cache and TLB misses in the L2
when HW_CACHE_REFERENCES and HW_CACHE_MISSES are enabled,
respectively. That way the events measure unified caches on both
platforms.

Signed-off-by: Matt Fleming <matt@codeblueprint.co.uk>
Acked-by: Peter Zijlstra <peterz@infradead.org>
Cc: <stable@vger.kernel.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/1472044328-21302-1-git-send-email-matt@codeblueprint.co.uk


Signed-off-by: Ingo Molnar <mingo@kernel.org>

parent 1155bafc

arch/x86/events/amd/core.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -119,8 +119,8 @@ static const u64 amd_perfmon_event_map[PERF_COUNT_HW_MAX] =
		{
		[PERF_COUNT_HW_CPU_CYCLES] = 0x0076,
		[PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
		[PERF_COUNT_HW_CACHE_REFERENCES] = 0x0080,
		[PERF_COUNT_HW_CACHE_MISSES] = 0x0081,
		[PERF_COUNT_HW_CACHE_REFERENCES] = 0x077d,
		[PERF_COUNT_HW_CACHE_MISSES] = 0x077e,
		[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c2,
		[PERF_COUNT_HW_BRANCH_MISSES] = 0x00c3,
		[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00d0, /* "Decoder empty" event */

arch/x86/kvm/pmu_amd.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -23,8 +23,8 @@
		static struct kvm_event_hw_type_mapping amd_event_mapping[] = {
		[0] = { 0x76, 0x00, PERF_COUNT_HW_CPU_CYCLES },
		[1] = { 0xc0, 0x00, PERF_COUNT_HW_INSTRUCTIONS },
		[2] = { 0x80, 0x00, PERF_COUNT_HW_CACHE_REFERENCES },
		[3] = { 0x81, 0x00, PERF_COUNT_HW_CACHE_MISSES },
		[2] = { 0x7d, 0x07, PERF_COUNT_HW_CACHE_REFERENCES },
		[3] = { 0x7e, 0x07, PERF_COUNT_HW_CACHE_MISSES },
		[4] = { 0xc2, 0x00, PERF_COUNT_HW_BRANCH_INSTRUCTIONS },
		[5] = { 0xc3, 0x00, PERF_COUNT_HW_BRANCH_MISSES },
		[6] = { 0xd0, 0x00, PERF_COUNT_HW_STALLED_CYCLES_FRONTEND },

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