Commit 07dd966d authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'omap-for-v5.11/genpd-am335x-signed' of... 

Merge tag 'omap-for-v5.11/genpd-am335x-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/omap-genpd

Update am335x to boot without platform data

With the driver updates done for genpd support, we can now update
am335x dts files to boot with genpd and simple-pm-bus, and drop
the related platform data.

To do that, we need to do the following changes for am335x:

- Add the remaining power domain and reset controller instances

- Configure interconnect clocks for system timers as those are
  now managed separately by the drivers/clocksource drivers

- Update control module, RTC, gpmc, debugss, emif, ocmcram,
  instr, and mpuss for device tree data and drop the legacy
  platform data

- Update the interconnect instances to boot with gendp and
  simple-pm-bus

- Drop the remaining platform data for am335x

- Add kconfig option for OMAP_HWMOD to build it only for the
  SoCs that need it

* tag 'omap-for-v5.11/genpd-am335x-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP2+: Build hwmod related code as needed
  ARM: OMAP2+: Drop legacy remaining legacy platform data for am3
  ARM: dts: Use simple-pm-bus for genpd for am3 l3
  ARM: dts: Use simple-pm-bus for genpd for am3 l4_per
  ARM: dts: Use simple-pm-bus for genpd for am3 l4_fast
  ARM: dts: Use simple-pm-bus for genpd for am3 l4_wkup
  ARM: OMAP2+: Drop legacy platform data for am3 mpuss
  ARM: OMAP2+: Drop legacy platform data for am3 instr
  ARM: OMAP2+: Drop legacy platform data for am3 ocmcram
  ARM: OMAP2+: Drop legacy platform data for am3 emif
  ARM: OMAP2+: Drop legacy platform data for am3 debugss
  ARM: OMAP2+: Drop legacy platform data for am3 and am4 gpmc
  ARM: OMAP2+: Drop legacy platform data for am3 wkup_m3
  ARM: dts: Configure interconnect target module for am3 wkup_m3
  ARM: dts: Configure RTC powerdomain for am3
  ARM: OMAP2+: Drop legacy platform data for am3 control module
  ARM: dts: Configure also interconnect clocks for am4 system timer
  ARM: dts: am33xx: add remaining PRM instances

Link: https://lore.kernel.org/r/pull-1606806458-694517@atomide.com-2


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 80c25006 133ad7ab

arch/arm/boot/dts/am335x-nano.dts

+0 −1
Original line number Diff line number Diff line
@@ -238,7 +238,6 @@ 


&gpmc {

	compatible = "ti,am3352-gpmc";

	ti,hwmods = "gpmc";

	status = "okay";

	gpmc,num-waitpins = <2>;

	pinctrl-names = "default";

arch/arm/boot/dts/am33xx-l4.dtsi

+55 −20
Original line number Diff line number Diff line 
&l4_wkup {						/* 0x44c00000 */

	compatible = "ti,am33xx-l4-wkup", "simple-bus";

	compatible = "ti,am33xx-l4-wkup", "simple-pm-bus";

	power-domains = <&prm_wkup>;

	clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>;

	clock-names = "fck";

	reg = <0x44c00000 0x800>,

	      <0x44c00800 0x800>,

	      <0x44c01000 0x400>,
@@ -12,7 +15,7 @@ 
		 <0x00200000 0x44e00000 0x100000>;	/* segment 2 */



	segment@0 {					/* 0x44c00000 */

		compatible = "simple-bus";

		compatible = "simple-pm-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x00000000 0x00000000 0x000800>,	/* ap 0 */
@@ -22,7 +25,7 @@ 
	};



	segment@100000 {					/* 0x44d00000 */

		compatible = "simple-bus";

		compatible = "simple-pm-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x00000000 0x00100000 0x004000>,	/* ap 4 */
@@ -34,23 +37,27 @@ 
			compatible = "ti,sysc-omap4", "ti,sysc";

			reg = <0x0 0x4>;

			reg-names = "rev";

			clocks = <&l4_wkup_aon_clkctrl AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL 0>;

			clock-names = "fck";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x0 0x4000>;

			status = "disabled";

		};

			ranges = <0x00000000 0x00000000 0x4000>,

				 <0x00080000 0x00080000 0x2000>;



		target-module@80000 {			/* 0x44d80000, ap 6 10.0 */

			compatible = "ti,sysc";

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x80000 0x2000>;

			wkup_m3: cpu@0 {

				compatible = "ti,am3352-wkup-m3";

				reg = <0x00000000 0x4000>,

				      <0x00080000 0x2000>;

				reg-names = "umem", "dmem";

				resets = <&prm_wkup 3>;

				reset-names = "rstctrl";

				ti,pm-firmware = "am335x-pm-firmware.elf";

			};

		};

	};



	segment@200000 {					/* 0x44e00000 */

		compatible = "simple-bus";

		compatible = "simple-pm-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x00000000 0x00200000 0x002000>,	/* ap 8 */
@@ -274,6 +281,9 @@ 
			compatible = "ti,sysc-omap4", "ti,sysc";

			reg = <0x10000 0x4>;

			reg-names = "rev";

			clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_CONTROL_CLKCTRL 0>;

			clock-names = "fck";

			ti,no-idle;

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x00000000 0x00010000 0x00010000>,
@@ -433,6 +443,7 @@ 
					<SYSC_IDLE_SMART>,

					<SYSC_IDLE_SMART_WKUP>;

			/* Domains (P, C): rtc_pwrdm, l4_rtc_clkdm */

			power-domains = <&prm_rtc>;

			clocks = <&l4_rtc_clkctrl AM3_L4_RTC_RTC_CLKCTRL 0>;

			clock-names = "fck";

			#address-cells = <1>;
@@ -658,7 +669,10 @@ 
};



&l4_fast {					/* 0x4a000000 */

	compatible = "ti,am33xx-l4-fast", "simple-bus";

	compatible = "ti,am33xx-l4-fast", "simple-pm-bus";

	power-domains = <&prm_per>;

	clocks = <&l4hs_clkctrl AM3_L4HS_L4_HS_CLKCTRL 0>;

	clock-names = "fck";

	reg = <0x4a000000 0x800>,

	      <0x4a000800 0x800>,

	      <0x4a001000 0x400>;
@@ -668,7 +682,7 @@ 
	ranges = <0x00000000 0x4a000000 0x1000000>;	/* segment 0 */



	segment@0 {					/* 0x4a000000 */

		compatible = "simple-bus";

		compatible = "simple-pm-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x00000000 0x00000000 0x000800>,	/* ap 0 */
@@ -837,7 +851,10 @@ 
};



&l4_per {						/* 0x48000000 */

	compatible = "ti,am33xx-l4-per", "simple-bus";

	compatible = "ti,am33xx-l4-per", "simple-pm-bus";

	power-domains = <&prm_per>;

	clocks = <&l4ls_clkctrl AM3_L4LS_L4_LS_CLKCTRL 0>;

	clock-names = "fck";

	reg = <0x48000000 0x800>,

	      <0x48000800 0x800>,

	      <0x48001000 0x400>,
@@ -855,7 +872,7 @@ 
		 <0x46400000 0x46400000 0x400000>;	/* l3 data port */



	segment@0 {					/* 0x48000000 */

		compatible = "simple-bus";

		compatible = "simple-pm-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x00000000 0x00000000 0x000800>,	/* ap 0 */
@@ -1466,7 +1483,7 @@ 
	};



	segment@100000 {					/* 0x48100000 */

		compatible = "simple-bus";

		compatible = "simple-pm-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x0008c000 0x0018c000 0x001000>,	/* ap 42 */
@@ -1850,13 +1867,31 @@ 
	};



	segment@200000 {					/* 0x48200000 */

		compatible = "simple-bus";

		compatible = "simple-pm-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x00000000 0x00200000 0x010000>;



		target-module@0 {

			compatible = "ti,sysc-omap4-simple", "ti,sysc";

			power-domains = <&prm_mpu>;

			clocks = <&mpu_clkctrl AM3_MPU_MPU_CLKCTRL 0>;

			clock-names = "fck";

			ti,no-idle;

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0 0 0x10000>;



			mpu@0 {

				compatible = "ti,omap3-mpu";

				pm-sram = <&pm_sram_code

					   &pm_sram_data>;

			};

		};

	};



	segment@300000 {					/* 0x48300000 */

		compatible = "simple-bus";

		compatible = "simple-pm-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x00000000 0x00300000 0x001000>,	/* ap 66 */

arch/arm/boot/dts/am33xx.dtsi

+126 −59
Original line number Diff line number Diff line
@@ -144,11 +144,28 @@ 
		};

	};



	pmu@4b000000 {

	target-module@4b000000 {

		compatible = "ti,sysc-omap4-simple", "ti,sysc";

		clocks = <&l3_clkctrl AM3_L3_L3_INSTR_CLKCTRL 0>;

		clock-names = "fck";

		ti,no-idle;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x0 0x4b000000 0x1000000>;



		target-module@140000 {

			compatible = "ti,sysc-omap4-simple", "ti,sysc";

			clocks = <&l3_aon_clkctrl AM3_L3_AON_DEBUGSS_CLKCTRL 0>;

			clock-names = "fck";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x140000 0xec0000>;



			pmu@0 {

				compatible = "arm,cortex-a8-pmu";

				interrupts = <3>;

		reg = <0x4b000000 0x1000000>;

		ti,hwmods = "debugss";

			};

		};

	};



	/*
@@ -157,12 +174,6 @@ 
	 */

	soc {

		compatible = "ti,omap-infra";

		mpu {

			compatible = "ti,omap3-mpu";

			ti,hwmods = "mpu";

			pm-sram = <&pm_sram_code

				   &pm_sram_data>;

		};

	};



	/*
@@ -173,21 +184,15 @@ 
	 * the whole bus hierarchy.

	 */

	ocp: ocp {

		compatible = "simple-bus";

		compatible = "simple-pm-bus";

		power-domains = <&prm_per>;

		clocks = <&l3_clkctrl AM3_L3_L3_MAIN_CLKCTRL 0>;

		clock-names = "fck";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;

		ti,hwmods = "l3_main";



		l4_wkup: interconnect@44c00000 {

			wkup_m3: wkup_m3@100000 {

				compatible = "ti,am3352-wkup-m3";

				reg = <0x100000 0x4000>,

				      <0x180000 0x2000>;

				reg-names = "umem", "dmem";

				ti,hwmods = "wkup_m3";

				ti,pm-firmware = "am335x-pm-firmware.elf";

			};

		};

		l4_per: interconnect@48000000 {

		};
@@ -458,10 +463,19 @@ 
			};

		};



		ocmcram: sram@40300000 {

		target-module@40300000 {

			compatible = "ti,sysc-omap4-simple", "ti,sysc";

			clocks = <&l3_clkctrl AM3_L3_OCMCRAM_CLKCTRL 0>;

			clock-names = "fck";

			ti,no-idle;

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0 0x40300000 0x10000>;



			ocmcram: sram@0 {

				compatible = "mmio-sram";

			reg = <0x40300000 0x10000>; /* 64k */

			ranges = <0x0 0x40300000 0x10000>;

				reg = <0 0x10000>; /* 64k */

				ranges = <0 0 0x10000>;

				#address-cells = <1>;

				#size-cells = <1>;
@@ -477,21 +491,47 @@ 
					pool;

				};

			};

		};



		target-module@4c000000 {

			compatible = "ti,sysc-omap4-simple", "ti,sysc";

			reg = <0x4c000000 0x4>;

			reg-names = "rev";

			clocks = <&l3_clkctrl AM3_L3_EMIF_CLKCTRL 0>;

			clock-names = "fck";

			ti,no-idle;

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x4c000000 0x1000000>;



		emif: emif@4c000000 {

			emif: emif@0 {

				compatible = "ti,emif-am3352";

			reg = <0x4c000000 0x1000000>;

			ti,hwmods = "emif";

				reg = <0 0x1000000>;

				interrupts = <101>;

				sram = <&pm_sram_code

					&pm_sram_data>;

			ti,no-idle;

			};

		};



		target-module@50000000 {

			compatible = "ti,sysc-omap2", "ti,sysc";

			reg = <0x50000000 4>,

			      <0x50000010 4>,

			      <0x50000014 4>;

			reg-names = "rev", "sysc", "syss";

			ti,sysc-sidle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_NO>,

					<SYSC_IDLE_SMART>;

			ti,syss-mask = <1>;

			clocks = <&l3s_clkctrl AM3_L3S_GPMC_CLKCTRL 0>;

			clock-names = "fck";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x50000000 0x50000000 0x00001000>, /* regs */

				 <0x00000000 0x00000000 0x40000000>; /* data */



			gpmc: gpmc@50000000 {

				compatible = "ti,am3352-gpmc";

			ti,hwmods = "gpmc";

			ti,no-idle-on-init;

				reg = <0x50000000 0x2000>;

				interrupts = <100>;

				dmas = <&edma 52 0>;
@@ -506,6 +546,7 @@ 
				#gpio-cells = <2>;

				status = "disabled";

			};

		};



		sham_target: target-module@53100000 {

			compatible = "ti,sysc-omap3-sham", "ti,sysc";
@@ -601,12 +642,20 @@ 
		compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";

		reg = <0xc00 0x100>;

		#reset-cells = <1>;

		#power-domain-cells = <0>;

	};



	prm_wkup: prm@d00 {

		compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";

		reg = <0xd00 0x100>;

		#reset-cells = <1>;

		#power-domain-cells = <0>;

	};



	prm_mpu: prm@e00 {

		compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";

		reg = <0xe00 0x100>;

		#power-domain-cells = <0>;

	};



	prm_device: prm@f00 {
@@ -615,16 +664,31 @@ 
		#reset-cells = <1>;

	};



	prm_rtc: prm@1000 {

		compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";

		reg = <0x1000 0x100>;

		#power-domain-cells = <0>;

	};



	prm_gfx: prm@1100 {

		compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";

		reg = <0x1100 0x100>;

		#power-domain-cells = <0>;

		#reset-cells = <1>;

	};



	prm_cefuse: prm@1200 {

		compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";

		reg = <0x1200 0x100>;

		#power-domain-cells = <0>;

	};

};



/* Preferred always-on timer for clocksource */

&timer1_target {

	clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>,

		 <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>;

	clock-names = "fck", "ick";

	ti,no-reset-on-init;

	ti,no-idle;

	timer@0 {
@@ -635,6 +699,9 @@ 


/* Preferred timer for clockevent */

&timer2_target {

	clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>,

		 <&l4ls_clkctrl AM3_L4LS_L4_LS_CLKCTRL 0>;

	clock-names = "fck", "ick";

	ti,no-reset-on-init;

	ti,no-idle;

	timer@0 {

arch/arm/boot/dts/am4372.dtsi

+33 −16
Original line number Diff line number Diff line
@@ -434,9 +434,25 @@ 
			ranges = <0x0 0x54400000 0x80000>;

		};



		target-module@50000000 {

			compatible = "ti,sysc-omap2", "ti,sysc";

			reg = <0x50000000 4>,

			      <0x50000010 4>,

			      <0x50000014 4>;

			reg-names = "rev", "sysc", "syss";

			ti,sysc-sidle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_NO>,

					<SYSC_IDLE_SMART>;

			ti,syss-mask = <1>;

			clocks = <&l3s_clkctrl AM4_L3S_GPMC_CLKCTRL 0>;

			clock-names = "fck";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x50000000 0x50000000 0x00001000>, /* regs */

				 <0x00000000 0x00000000 0x40000000>; /* data */



			gpmc: gpmc@50000000 {

				compatible = "ti,am3352-gpmc";

			ti,hwmods = "gpmc";

				dmas = <&edma 52 0>;

				dma-names = "rxtx";

				clocks = <&l3s_gclk>;
@@ -453,6 +469,7 @@ 
				#gpio-cells = <2>;

				status = "disabled";

			};

		};



		target-module@47900000 {

			compatible = "ti,sysc-omap4", "ti,sysc";

arch/arm/mach-omap2/Kconfig

+9 −0
Original line number Diff line number Diff line
@@ -2,11 +2,15 @@ 
menu "TI OMAP/AM/DM/DRA Family"

	depends on ARCH_MULTI_V6 || ARCH_MULTI_V7



config OMAP_HWMOD

	bool



config ARCH_OMAP2

	bool "TI OMAP2"

	depends on ARCH_MULTI_V6

	select ARCH_OMAP2PLUS

	select CPU_V6

	select OMAP_HWMOD

	select SOC_HAS_OMAP2_SDRC



config ARCH_OMAP3
@@ -14,6 +18,7 @@ config ARCH_OMAP3 
	depends on ARCH_MULTI_V7

	select ARCH_OMAP2PLUS

	select ARM_CPU_SUSPEND if PM

	select OMAP_HWMOD

	select OMAP_INTERCONNECT

	select PM_OPP if PM

	select PM if CPU_IDLE
@@ -30,6 +35,7 @@ config ARCH_OMAP4 
	select ARM_GIC

	select HAVE_ARM_SCU if SMP

	select HAVE_ARM_TWD if SMP

	select OMAP_HWMOD

	select OMAP_INTERCONNECT

	select OMAP_INTERCONNECT_BARRIER

	select PL310_ERRATA_588369 if CACHE_L2X0
@@ -49,6 +55,7 @@ config SOC_OMAP5 
	select HAVE_ARM_SCU if SMP

	select HAVE_ARM_ARCH_TIMER

	select ARM_ERRATA_798181 if SMP

	select OMAP_HWMOD

	select OMAP_INTERCONNECT

	select OMAP_INTERCONNECT_BARRIER

	select PM_OPP if PM
@@ -71,6 +78,7 @@ config SOC_AM43XX 
	select HAVE_ARM_TWD

	select ARM_ERRATA_754322

	select ARM_ERRATA_775420

	select OMAP_HWMOD

	select OMAP_INTERCONNECT

	select ARM_CPU_SUSPEND if PM
@@ -84,6 +92,7 @@ config SOC_DRA7XX 
	select HAVE_ARM_ARCH_TIMER

	select IRQ_CROSSBAR

	select ARM_ERRATA_798181 if SMP

	select OMAP_HWMOD

	select OMAP_INTERCONNECT

	select OMAP_INTERCONNECT_BARRIER

	select PM_OPP if PM

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