Commit 07d79fe7 authored Oct 31, 2017 by Dave Martin Committed by Will Deacon Nov 03, 2017

arm64/sve: KVM: Hide SVE from CPU features exposed to guests



KVM guests cannot currently use SVE, because SVE is always
configured to trap to EL2.

However, a guest that sees SVE reported as present in
ID_AA64PFR0_EL1 may legitimately expect that SVE works and try to
use it.  Instead of working, the guest will receive an injected
undef exception, which may cause the guest to oops or go into a
spin.

To avoid misleading the guest into believing that SVE will work,
this patch masks out the SVE field from ID_AA64PFR0_EL1 when a
guest attempts to read this register.  No support is explicitly
added for ID_AA64ZFR0_EL1 either, so that is still emulated as
reading as zero, which is consistent with SVE not being
implemented.

This is a temporary measure, and will be removed in a later series
when full KVM support for SVE is implemented.

Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>

parent aac45ffd

arch/arm64/kvm/sys_regs.c

+11 −1

Original line number	Diff line number	Diff line
		@@ -23,6 +23,7 @@
		#include <linux/bsearch.h>
		#include <linux/kvm_host.h>
		#include <linux/mm.h>
		#include <linux/printk.h>
		#include <linux/uaccess.h>

		#include <asm/cacheflush.h>
		@@ -897,8 +898,17 @@ static u64 read_id_reg(struct sys_reg_desc const *r, bool raz)
		{
		u32 id = sys_reg((u32)r->Op0, (u32)r->Op1,
		(u32)r->CRn, (u32)r->CRm, (u32)r->Op2);
		u64 val = raz ? 0 : read_sanitised_ftr_reg(id);

		return raz ? 0 : read_sanitised_ftr_reg(id);
		if (id == SYS_ID_AA64PFR0_EL1) {
		if (val & (0xfUL << ID_AA64PFR0_SVE_SHIFT))
		pr_err_once("kvm [%i]: SVE unsupported for guests, suppressing\n",
		task_pid_nr(current));

		val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT);
		}

		return val;
		}

		/* cpufeature ID register access trap handlers */

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