Commit 078086f3 authored by Rasesh Mody's avatar Rasesh Mody Committed by David S. Miller
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bna: ENET and Tx Rx Redesign Enablement 



Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
 - structure and function definition changes to header files as a result
   of Ethport, Enet, IOCEth, Tx, Rx redesign.
 - ethtool changes to use new enet function and definitions
 - Set number of Tx and Rx queues bassed on underlying hardware. Define
   separate macros for maximum and supported numbers of Tx and Rx queues
   based on underlying hardware. Take VLAN header into account for MTU
   calculation. Default to INTx mode when pci_enable_msix() fails. Set a
   bit in Rx poll routine, check and wait for that bit to be cleared in
   the cleanup routine before proceeding.
 - The TX and Rx coalesce settings are programmed in steps of 5 us. The value
   that are not divisible by 5 are rounded to the next lower number. This was
   causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
   When creating Rx and Tx object, we are currently assigning the default
   values of Rx and Tx coalescing_timeo. If these values are changed in the
   driver to a different value, the change is lost during such operations as
   MTU change. In order to avoid that, pass the configured value of
   coalescing_timeo before Rx and Tx object creation. Fix
   bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
 - Reorg uninitialization path in case of pci_probe failure.
 - Hardware clock setup changes to pass asic generation, port modes and
   asic mode as part firmware boot parameters to firmware.
 - FW mailbox interface changes to defined asic specific mailbox interfaces.
   h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
   up mailbox definitions and usage for new and old HW. Eliminated usage of
   ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
   host offsets for CPE/RME queue registers.
 - Implement polling mechanism for FW ready to have poll mechanism replaces
   the current interrupt based FW READY method. The timer based poll routine
   in IOC will query the ioc_fwstate register to see if there is a state
   change in FW, and sends the READY event. Removed infrastructure needed to
   support mbox READY event from fw as well as IOC code.
 - Move FW init to HW init. Handle the case where PCI mapping goes away when
   IOCPF state machine is waiting for semaphore.
 - Add IOC mbox call back to client indicating that the command is sent.

Signed-off-by: default avatarRasesh Mody <rmody@brocade.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 6849c6b3

drivers/net/ethernet/brocade/bna/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -5,7 +5,7 @@ 


obj-$(CONFIG_BNA) += bna.o



bna-objs := bnad.o bnad_ethtool.o bna_ctrl.o bna_txrx.o

bna-objs := bnad.o bnad_ethtool.o bna_enet.o bna_tx_rx.o

bna-objs += bfa_msgq.o bfa_ioc.o bfa_ioc_ct.o bfa_cee.o

bna-objs += cna_fwimg.o

drivers/net/ethernet/brocade/bna/bfa_defs.h

+22 −3
Original line number Diff line number Diff line
@@ -124,6 +124,7 @@ enum bfa_ioc_state { 
	BFA_IOC_DISABLED	= 10,	/*!< IOC is disabled */

	BFA_IOC_FWMISMATCH	= 11,	/*!< IOC f/w different from drivers */

	BFA_IOC_ENABLING	= 12,	/*!< IOC is being enabled */

	BFA_IOC_HWFAIL		= 13,	/*!< PCI mapping doesn't exist */

};



/**
@@ -180,7 +181,18 @@ struct bfa_ioc_attr { 
	struct bfa_ioc_driver_attr driver_attr;	/*!< driver attr    */

	struct bfa_ioc_pci_attr pci_attr;

	u8				port_id;	/*!< port number */

	u8				rsvd[7];	/*!< 64bit align    */

	u8				port_mode;	/*!< enum bfa_mode */

	u8				cap_bm;		/*!< capability */

	u8				port_mode_cfg;	/*!< enum bfa_mode */

	u8				rsvd[4];	/*!< 64bit align */

};



/**

 * Adapter capability mask definition

 */

enum {

	BFA_CM_HBA	=	0x01,

	BFA_CM_CNA	=	0x02,

};



/**
@@ -228,7 +240,7 @@ struct bfa_mfg_block { 
	mac_t		mfg_mac;	/*!< mac address */

	u8		num_mac;	/*!< number of mac addresses */

	u8		rsv2;

	u32	mfg_type;	/*!< card type */

	u32		card_type;	/*!< card type */

	u8		rsv3[108];

	u8		md5_chksum[BFA_MFG_CHKSUM_SIZE]; /*!< md5 checksum */

};
@@ -242,5 +254,12 @@ struct bfa_mfg_block { 
#define bfa_asic_id_ct(devid)			\

	((devid) == PCI_DEVICE_ID_BROCADE_CT ||	\

	(devid) == PCI_DEVICE_ID_BROCADE_CT_FC)

#define bfa_asic_id_ctc(devid) (bfa_asic_id_ct(devid))



enum bfa_mode {

	BFA_MODE_HBA		= 1,

	BFA_MODE_CNA		= 2,

	BFA_MODE_NIC		= 3

};



#endif /* __BFA_DEFS_H__ */

drivers/net/ethernet/brocade/bna/bfa_defs_mfg_comm.h

+4 −16
Original line number Diff line number Diff line
@@ -19,11 +19,12 @@ 
#define __BFA_DEFS_MFG_COMM_H__



#include "cna.h"

#include "bfa_defs.h"



/**

 * Manufacturing block version

 */

#define BFA_MFG_VERSION				2

#define BFA_MFG_VERSION				3

#define BFA_MFG_VERSION_UNINIT			0xFF



/**
@@ -95,27 +96,14 @@ enum { 
	(type) == BFA_MFG_TYPE_CNA10P1 || \

	bfa_mfg_is_mezz(type)))



#define bfa_mfg_adapter_prop_init_flash(card_type, prop)	\

#define bfa_mfg_adapter_prop_init_flash_ct(mfgblk, prop)	\

do {								\

	switch ((card_type)) {					\

	case BFA_MFG_TYPE_FC8P2:				\

	switch ((mfgblk)->card_type) {				\

	case BFA_MFG_TYPE_JAYHAWK:				\

	case BFA_MFG_TYPE_ASTRA:				\

		(prop) = BFI_ADAPTER_SETP(NPORTS, 2) |		\

			BFI_ADAPTER_SETP(SPEED, 8);		\

		break;						\

	case BFA_MFG_TYPE_FC8P1:				\

		(prop) = BFI_ADAPTER_SETP(NPORTS, 1) |		\

			BFI_ADAPTER_SETP(SPEED, 8);		\

		break;						\

	case BFA_MFG_TYPE_FC4P2:				\

		(prop) = BFI_ADAPTER_SETP(NPORTS, 2) |		\

			BFI_ADAPTER_SETP(SPEED, 4);		\

		break;						\

	case BFA_MFG_TYPE_FC4P1:				\

		(prop) = BFI_ADAPTER_SETP(NPORTS, 1) |		\

			BFI_ADAPTER_SETP(SPEED, 4);		\

		break;						\

	case BFA_MFG_TYPE_CNA10P2:				\

	case BFA_MFG_TYPE_WANCHESE:				\

	case BFA_MFG_TYPE_LIGHTNING_P0:				\

drivers/net/ethernet/brocade/bna/bfa_ioc.c

+253 −136

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drivers/net/ethernet/brocade/bna/bfa_ioc.h

+26 −10

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