Commit 077f46db authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'v5.5-rockchip-dts64-2' of... 

Merge tag 'v5.5-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt

One new soc the rk3308 with quad-Cortex-A35 cores.
New boards are Beelink A1, roc-rk3308-cc, rk3308-evb
A big number of improvements for the rk3399-roc-pc board
(support for M.2 variant, reworked power-tree, buttons, leds)
and further improvements of the px30-evb (usb2phy, otp controller,
removal of default optee node - optee does add its own when loaded)
And finally rk3328 audio support, sdmmc detection fix and enabled
of the gpu on rk3399-puma.

* tag 'v5.5-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (21 commits)
  arm64: dts: rockchip: fix sdmmc detection on boot on rk3328-roc-cc
  arm64: dts: rockchip: Split rk3399-roc-pc for with and without mezzanine board.
  arm64: dts: rockchip: Add Beelink A1
  dt-bindings: ARM: rockchip: Add Beelink A1
  arm64: dts: rockchip: Add RK3328 audio pipelines
  arm64: dts: rockchip: Add devicetree for board roc-rk3308-cc
  dt-bindings: Add doc for Firefly ROC-RK3308-CC board
  dt-bindings: clean up rockchip grf binding document
  arm64: dts: rockchip: Rework voltage supplies for regulators on rk3399-roc-pc
  arm64: dts: rockchip: Add vcc_sys enable pin on rk3399-roc-pc
  arm64: dts: rockchip: Add nodes for buttons on rk3399-roc-pc
  arm64: dts: rockchip: enable usb2phy on px30-evb
  arm64: dts: rockchip: add usb2phy for px30
  arm64: dts: rockchip: remove px30 default optee node
  arm64: dts: rockchip: enable gpu on rk3399-puma
  arm64: dts: rockchip: add px30 otp controller
  arm64: dts: rockchip: Add LED nodes on rk3399-roc-pc
  arm64: dts: rockchip: Add basic dts for RK3308 EVB
  dt-bindings: Add doc for rk3308-evb
  arm64: dts: rockchip: Add core dts for RK3308 SOC
  ...

Link: https://lore.kernel.org/r/12204771.K8DX0fml49@phil


Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 4ed56fca 75aa5678

Documentation/devicetree/bindings/arm/rockchip.yaml

+18 −1
Original line number Diff line number Diff line
@@ -40,6 +40,11 @@ properties: 
          - const: asus,rk3288-tinker-s

          - const: rockchip,rk3288



      - description: Beelink A1

        items:

          - const: azw,beelink-a1

          - const: rockchip,rk3328



      - description: bq Curie 2 tablet

        items:

          - const: mundoreader,bq-curie2
@@ -82,6 +87,11 @@ properties: 
          - const: firefly,firefly-rk3399

          - const: rockchip,rk3399



      - description: Firefly ROC-RK3308-CC

        items:

          - const: firefly,roc-rk3308-cc

          - const: rockchip,rk3308



      - description: Firefly roc-rk3328-cc

        items:

          - const: firefly,roc-rk3328-cc
@@ -89,7 +99,9 @@ properties: 


      - description: Firefly ROC-RK3399-PC

        items:

          - const: firefly,roc-rk3399-pc

          - enum:

              - firefly,roc-rk3399-pc

              - firefly,roc-rk3399-pc-mezzanine

          - const: rockchip,rk3399



      - description: FriendlyElec NanoPi4 series boards
@@ -464,6 +476,11 @@ properties: 
              - rockchip,rk3288-evb-rk808

          - const: rockchip,rk3288



      - description: Rockchip RK3308 Evaluation board

        items:

          - const: rockchip,rk3308-evb

          - const: rockchip,rk3308



      - description: Rockchip RK3328 Evaluation board

        items:

          - const: rockchip,rk3328-evb

Documentation/devicetree/bindings/soc/rockchip/grf.txt

+14 −3
Original line number Diff line number Diff line
@@ -10,6 +10,12 @@ From RK3368 SoCs, the GRF is divided into two sections, 


On RK3328 SoCs, the GRF adds a section for USB2PHYGRF,



ON RK3308 SoC, the GRF is divided into four sections:

- GRF, used for general non-secure system,

- SGRF, used for general secure system,

- DETECTGRF, used for audio codec system,

- COREGRF, used for pvtm,



Required Properties:



- compatible: GRF should be one of the following:
@@ -19,20 +25,25 @@ Required Properties: 
   - "rockchip,rk3188-grf", "syscon": for rk3188

   - "rockchip,rk3228-grf", "syscon": for rk3228

   - "rockchip,rk3288-grf", "syscon": for rk3288

   - "rockchip,rk3308-grf", "syscon": for rk3308

   - "rockchip,rk3328-grf", "syscon": for rk3328

   - "rockchip,rk3368-grf", "syscon": for rk3368

   - "rockchip,rk3399-grf", "syscon": for rk3399

   - "rockchip,rv1108-grf", "syscon": for rv1108

- compatible: DETECTGRF should be one of the following:

   - "rockchip,rk3308-detect-grf", "syscon": for rk3308

- compatilbe: COREGRF should be one of the following:

   - "rockchip,rk3308-core-grf", "syscon": for rk3308

- compatible: PMUGRF should be one of the following:

   - "rockchip,px30-pmugrf", "syscon": for px30

   - "rockchip,rk3368-pmugrf", "syscon": for rk3368

   - "rockchip,rk3399-pmugrf", "syscon": for rk3399

- compatible: SGRF should be one of the following

- compatible: SGRF should be one of the following:

   - "rockchip,rk3288-sgrf", "syscon": for rk3288

- compatible: USB2PHYGRF should be one of the followings

- compatible: USB2PHYGRF should be one of the following:

   - "rockchip,px30-usb2phy-grf", "syscon": for px30

   - "rockchip,rk3328-usb2phy-grf", "syscon": for rk3328

- compatible: USBGRF should be one of the following

- compatible: USBGRF should be one of the following:

   - "rockchip,rv1108-usbgrf", "syscon": for rv1108

- reg: physical base address of the controller and length of memory mapped

  region.

arch/arm64/boot/dts/rockchip/Makefile

+4 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb

dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb.dtb

dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-roc-cc.dtb

dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb

dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb

dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb

dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
@@ -27,6 +30,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-neo4.dtb 
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-orangepi.dtb

dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb

dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb

dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-mezzanine.dtb

dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4.dtb

dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock960.dtb

dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64.dtb

arch/arm64/boot/dts/rockchip/px30-evb.dts

+12 −0
Original line number Diff line number Diff line
@@ -485,6 +485,18 @@ 
	status = "okay";

};



&u2phy {

	status = "okay";



	u2phy_host: host-port {

		status = "okay";

	};



	u2phy_otg: otg-port {

		status = "okay";

	};

};



&uart1 {

	pinctrl-names = "default";

	pinctrl-0 = <&uart1_xfer &uart1_cts>;

arch/arm64/boot/dts/rockchip/px30.dtsi

+67 −7
Original line number Diff line number Diff line
@@ -161,13 +161,6 @@ 
		status = "disabled";

	};



	firmware {

		optee {

			compatible = "linaro,optee-tz";

			method = "smc";

		};

	};



	gmac_clkin: external-gmac-clock {

		compatible = "fixed-clock";

		clock-frequency = <50000000>;
@@ -664,6 +657,30 @@ 
		status = "disabled";

	};



	otp: nvmem@ff290000 {

		compatible = "rockchip,px30-otp";

		reg = <0x0 0xff290000 0x0 0x4000>;

		clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,

			 <&cru PCLK_OTP_PHY>;

		clock-names = "otp", "apb_pclk", "phy";

		resets = <&cru SRST_OTP_PHY>;

		reset-names = "phy";

		#address-cells = <1>;

		#size-cells = <1>;



		/* Data cells */

		cpu_id: id@7 {

			reg = <0x07 0x10>;

		};

		cpu_leakage: cpu-leakage@17 {

			reg = <0x17 0x1>;

		};

		performance: performance@1e {

			reg = <0x1e 0x1>;

			bits = <4 3>;

		};

	};



	cru: clock-controller@ff2b0000 {

		compatible = "rockchip,px30-cru";

		reg = <0x0 0xff2b0000 0x0 0x1000>;
@@ -701,6 +718,43 @@ 
			<26000000>;

	};



	usb2phy_grf: syscon@ff2c0000 {

		compatible = "rockchip,px30-usb2phy-grf", "syscon",

			     "simple-mfd";

		reg = <0x0 0xff2c0000 0x0 0x10000>;

		#address-cells = <1>;

		#size-cells = <1>;



		u2phy: usb2-phy@100 {

			compatible = "rockchip,px30-usb2phy";

			reg = <0x100 0x20>;

			clocks = <&pmucru SCLK_USBPHY_REF>;

			clock-names = "phyclk";

			#clock-cells = <0>;

			assigned-clocks = <&cru USB480M>;

			assigned-clock-parents = <&u2phy>;

			clock-output-names = "usb480m_phy";

			status = "disabled";



			u2phy_host: host-port {

				#phy-cells = <0>;

				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;

				interrupt-names = "linestate";

				status = "disabled";

			};



			u2phy_otg: otg-port {

				#phy-cells = <0>;

				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;

				interrupt-names = "otg-bvalid", "otg-id",

						  "linestate";

				status = "disabled";

			};

		};

	};



	usb20_otg: usb@ff300000 {

		compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",

			     "snps,dwc2";
@@ -713,6 +767,8 @@ 
		g-rx-fifo-size = <280>;

		g-tx-fifo-size = <256 128 128 64 32 16>;

		g-use-dma;

		phys = <&u2phy_otg>;

		phy-names = "usb2-phy";

		power-domains = <&power PX30_PD_USB>;

		status = "disabled";

	};
@@ -723,6 +779,8 @@ 
		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru HCLK_HOST>;

		clock-names = "usbhost";

		phys = <&u2phy_host>;

		phy-names = "usb";

		power-domains = <&power PX30_PD_USB>;

		status = "disabled";

	};
@@ -733,6 +791,8 @@ 
		interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru HCLK_HOST>;

		clock-names = "usbhost";

		phys = <&u2phy_host>;

		phy-names = "usb";

		power-domains = <&power PX30_PD_USB>;

		status = "disabled";

	};

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