Commit 074e9915 authored by Swapnil Jakhade's avatar Swapnil Jakhade Committed by Vinod Koul
Browse files

dt-bindings: phy: cadence-torrent: Update Torrent PHY bindings for generic use



Torrent PHY can be used in different multi-link multi-protocol
configurations including protocols other than DisplayPort also,
such as PCIe, USB, SGMII, QSGMII etc. Update the bindings to have
support for these configurations.

Signed-off-by: default avatarSwapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600280911-9214-8-git-send-email-sjakhade@cadence.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 962fad30
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+60 −17
Original line number Diff line number Diff line
@@ -4,11 +4,13 @@
$id: "http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Cadence Torrent SD0801 PHY binding for DisplayPort
title: Cadence Torrent SD0801 PHY binding

description:
  This binding describes the Cadence SD0801 PHY (also known as Torrent PHY)
  hardware included with the Cadence MHDP DisplayPort controller.
  hardware included with the Cadence MHDP DisplayPort controller. Torrent
  PHY also supports multilink multiprotocol combinations including protocols
  such as PCIe, USB, SGMII, QSGMII etc.

maintainers:
  - Swapnil Jakhade <sjakhade@cadence.com>
@@ -49,13 +51,14 @@ properties:
      - const: dptx_phy

  resets:
    maxItems: 1
    description:
      Torrent PHY reset.
      See Documentation/devicetree/bindings/reset/reset.txt
    minItems: 1
    maxItems: 2
    items:
      - description: Torrent PHY reset.
      - description: Torrent APB reset. This is optional.

patternProperties:
  '^phy@[0-7]+$':
  '^phy@[0-3]$':
    type: object
    description:
      Each group of PHY lanes with a single master lane should be represented as a sub-node.
@@ -63,6 +66,8 @@ patternProperties:
      reg:
        description:
          The master lane number. This is the lowest numbered lane in the lane group.
        minimum: 0
        maximum: 3

      resets:
        minItems: 1
@@ -78,13 +83,14 @@ patternProperties:
          Specifies the type of PHY for which the group of PHY lanes is used.
          Refer include/dt-bindings/phy/phy.h. Constants from the header should be used.
        $ref: /schemas/types.yaml#/definitions/uint32
        enum: [1, 2, 3, 4, 5, 6]
        minimum: 1
        maximum: 9

      cdns,num-lanes:
        description:
          Number of DisplayPort lanes.
          Number of lanes.
        $ref: /schemas/types.yaml#/definitions/uint32
        enum: [1, 2, 4]
        enum: [1, 2, 3, 4]
        default: 4

      cdns,ssc-mode:
@@ -108,6 +114,7 @@ patternProperties:
      - resets
      - "#phy-cells"
      - cdns,phy-type
      - cdns,num-lanes

    additionalProperties: false

@@ -152,4 +159,40 @@ examples:
            };
        };
    };
  - |
    #include <dt-bindings/phy/phy.h>
    #include <dt-bindings/phy/phy-cadence-torrent.h>

    bus {
        #address-cells = <2>;
        #size-cells = <2>;

        torrent-phy@f0fb500000 {
            compatible = "cdns,torrent-phy";
            reg = <0xf0 0xfb500000 0x0 0x00100000>;
            reg-names = "torrent_phy";
            resets = <&phyrst 0>, <&phyrst 1>;
            clocks = <&ref_clk>;
            clock-names = "refclk";
            #address-cells = <1>;
            #size-cells = <0>;
            phy@0 {
                reg = <0>;
                resets = <&phyrst 2>, <&phyrst 3>;
                #phy-cells = <0>;
                cdns,phy-type = <PHY_TYPE_PCIE>;
                cdns,num-lanes = <2>;
                cdns,ssc-mode = <TORRENT_SERDES_NO_SSC>;
            };

            phy@2 {
                reg = <2>;
                resets = <&phyrst 4>;
                #phy-cells = <0>;
                cdns,phy-type = <PHY_TYPE_SGMII>;
                cdns,num-lanes = <1>;
                cdns,ssc-mode = <TORRENT_SERDES_NO_SSC>;
            };
        };
    };
...