Merge tag 'omap-for-v3.20/cleanup-pt1' of... (074450e4) · Commits · 戴 / test

arch/arm/mach-omap1/irq.c

+0 −5

Original line number	Diff line number	Diff line
		@@ -64,11 +64,6 @@ u32 omap_irq_flags;
		static unsigned int irq_bank_count;
		static struct omap_irq_bank *irq_banks;

		static inline unsigned int irq_bank_readl(int bank, int offset)
		{
		return omap_readl(irq_banks[bank].base_reg + offset);
		}

		static inline void irq_bank_writel(unsigned long value, int bank, int offset)
		{
		omap_writel(value, irq_banks[bank].base_reg + offset);

arch/arm/mach-omap1/timer32k.c

+0 −5

Original line number	Diff line number	Diff line
		@@ -91,11 +91,6 @@ static inline void omap_32k_timer_write(int val, int reg)
		omap_writew(val, OMAP1_32K_TIMER_BASE + reg);
		}

		static inline unsigned long omap_32k_timer_read(int reg)
		{
		return omap_readl(OMAP1_32K_TIMER_BASE + reg) & 0xffffff;
		}

		static inline void omap_32k_timer_start(unsigned long load_val)
		{
		if (!load_val)

arch/arm/mach-omap2/Makefile

+0 −1

Original line number	Diff line number	Diff line
		@@ -181,7 +181,6 @@ obj-$(CONFIG_SOC_DRA7XX) += clockdomains7xx_data.o
		obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
		obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o
		obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o
		obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o
		obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o
		obj-$(CONFIG_SOC_OMAP2430) += clock2430.o
		obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o

arch/arm/mach-omap2/cclock3xxx_data.c

+1 −5

Original line number	Diff line number	Diff line
		@@ -3634,10 +3634,6 @@ int __init omap3xxx_clk_init(void)
		omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
		ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
		omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks));
		} else if (soc_is_am33xx()) {
		cpu_mask = RATE_IN_AM33XX;
		} else if (cpu_is_ti814x()) {
		cpu_mask = RATE_IN_TI814X;
		} else if (cpu_is_omap34xx()) {
		if (omap_rev() == OMAP3430_REV_ES1_0) {
		cpu_mask = RATE_IN_3430ES1;
		@@ -3681,7 +3677,7 @@ int __init omap3xxx_clk_init(void)
		* Lock DPLL5 -- here only until other device init code can
		* handle this
		*/
		if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0))
		if (omap_rev() >= OMAP3430_REV_ES2_0)
		omap3_clk_lock_dpll5();

		/* Avoid sleeping during omap3_core_dpll_m2_set_rate() */

arch/arm/mach-omap2/clkt2xxx_apll.c

deleted100644 → 0

+0 −142

Original line number	Diff line number	Diff line
		/*
		* OMAP2xxx APLL clock control functions
		*
		* Copyright (C) 2005-2008 Texas Instruments, Inc.
		* Copyright (C) 2004-2010 Nokia Corporation
		*
		* Contacts:
		* Richard Woodruff <r-woodruff2@ti.com>
		* Paul Walmsley
		*
		* Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
		* Gordon McNutt and RidgeRun, Inc.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 as
		* published by the Free Software Foundation.
		*/
		#undef DEBUG

		#include <linux/kernel.h>
		#include <linux/clk.h>
		#include <linux/io.h>


		#include "clock.h"
		#include "clock2xxx.h"
		#include "cm2xxx.h"
		#include "cm-regbits-24xx.h"

		/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
		#define EN_APLL_STOPPED 0
		#define EN_APLL_LOCKED 3

		/* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
		#define APLLS_CLKIN_19_2MHZ 0
		#define APLLS_CLKIN_13MHZ 2
		#define APLLS_CLKIN_12MHZ 3

		/* Private functions */

		/**
		* omap2xxx_clk_apll_locked - is the APLL locked?
		* @hw: struct clk_hw * of the APLL to check
		*
		* If the APLL IP block referred to by @hw indicates that it's locked,
		* return true; otherwise, return false.
		*/
		static bool omap2xxx_clk_apll_locked(struct clk_hw *hw)
		{
		struct clk_hw_omap *clk = to_clk_hw_omap(hw);
		u32 r, apll_mask;

		apll_mask = EN_APLL_LOCKED << clk->enable_bit;

		r = omap2xxx_cm_get_pll_status();

		return ((r & apll_mask) == apll_mask) ? true : false;
		}

		int omap2_clk_apll96_enable(struct clk_hw *hw)
		{
		return omap2xxx_cm_apll96_enable();
		}

		int omap2_clk_apll54_enable(struct clk_hw *hw)
		{
		return omap2xxx_cm_apll54_enable();
		}

		static void _apll96_allow_idle(struct clk_hw_omap *clk)
		{
		omap2xxx_cm_set_apll96_auto_low_power_stop();
		}

		static void _apll96_deny_idle(struct clk_hw_omap *clk)
		{
		omap2xxx_cm_set_apll96_disable_autoidle();
		}

		static void _apll54_allow_idle(struct clk_hw_omap *clk)
		{
		omap2xxx_cm_set_apll54_auto_low_power_stop();
		}

		static void _apll54_deny_idle(struct clk_hw_omap *clk)
		{
		omap2xxx_cm_set_apll54_disable_autoidle();
		}

		void omap2_clk_apll96_disable(struct clk_hw *hw)
		{
		omap2xxx_cm_apll96_disable();
		}

		void omap2_clk_apll54_disable(struct clk_hw *hw)
		{
		omap2xxx_cm_apll54_disable();
		}

		unsigned long omap2_clk_apll54_recalc(struct clk_hw *hw,
		unsigned long parent_rate)
		{
		return (omap2xxx_clk_apll_locked(hw)) ? 54000000 : 0;
		}

		unsigned long omap2_clk_apll96_recalc(struct clk_hw *hw,
		unsigned long parent_rate)
		{
		return (omap2xxx_clk_apll_locked(hw)) ? 96000000 : 0;
		}

		/* Public data */
		const struct clk_hw_omap_ops clkhwops_apll54 = {
		.allow_idle = _apll54_allow_idle,
		.deny_idle = _apll54_deny_idle,
		};

		const struct clk_hw_omap_ops clkhwops_apll96 = {
		.allow_idle = _apll96_allow_idle,
		.deny_idle = _apll96_deny_idle,
		};

		/* Public functions */

		u32 omap2xxx_get_apll_clkin(void)
		{
		u32 aplls, srate = 0;

		aplls = omap2xxx_cm_get_pll_config();
		aplls &= OMAP24XX_APLLS_CLKIN_MASK;
		aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;

		if (aplls == APLLS_CLKIN_19_2MHZ)
		srate = 19200000;
		else if (aplls == APLLS_CLKIN_13MHZ)
		srate = 13000000;
		else if (aplls == APLLS_CLKIN_12MHZ)
		srate = 12000000;

		return srate;
		}

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