Commit 0727e40a authored by Paulo Zanoni's avatar Paulo Zanoni
Browse files

drm/i915/gen9: fix the WaWmMemoryReadLatency implementation 



Bspec says:
  "The mailbox response data may not account for memory read latency.
   If the mailbox response data for level 0 is 0us, add 2 microseconds
   to the result for each valid level."

This means we should only do the +2 in case wm[0] == 0, not always.

So split the sanitizing implementation from the WA implementation and
fix the WA implementation.

v2: Add Fixes tag (Maarten).

Fixes: 367294be ("drm/i915/gen9: Add 2us read latency to WM level")
Cc: stable@vger.kernel.org
Cc: Vandana Kannan <vandana.kannan@intel.com>
Reviewed-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1474578035-424-5-git-send-email-paulo.r.zanoni@intel.com
parent 6e3100ec

drivers/gpu/drm/i915/intel_pm.c

+22 −20
Original line number Diff line number Diff line
@@ -2126,33 +2126,35 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8]) 
		wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &

				GEN9_MEM_LATENCY_LEVEL_MASK;



		/*

		 * If a level n (n > 1) has a 0us latency, all levels m (m >= n)

		 * need to be disabled. We make sure to sanitize the values out

		 * of the punit to satisfy this requirement.

		 */

		for (level = 1; level <= max_level; level++) {

			if (wm[level] == 0) {

				for (i = level + 1; i <= max_level; i++)

					wm[i] = 0;

				break;

			}

		}



		/*

		 * WaWmMemoryReadLatency:skl

		 *

		 * punit doesn't take into account the read latency so we need

		 * to add 2us to the various latency levels we retrieve from

		 * the punit.

		 *   - W0 is a bit special in that it's the only level that

		 *   can't be disabled if we want to have display working, so

		 *   we always add 2us there.

		 *   - For levels >=1, punit returns 0us latency when they are

		 *   disabled, so we respect that and don't add 2us then

		 *

		 * Additionally, if a level n (n > 1) has a 0us latency, all

		 * levels m (m >= n) need to be disabled. We make sure to

		 * sanitize the values out of the punit to satisfy this

		 * requirement.

		 * to add 2us to the various latency levels we retrieve from the

		 * punit when level 0 response data us 0us.

		 */

		if (wm[0] == 0) {

			wm[0] += 2;

		for (level = 1; level <= max_level; level++)

			if (wm[level] != 0)

				wm[level] += 2;

			else {

				for (i = level + 1; i <= max_level; i++)

					wm[i] = 0;



			for (level = 1; level <= max_level; level++) {

				if (wm[level] == 0)

					break;

				wm[level] += 2;

			}

		}



	} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {

		uint64_t sskpd = I915_READ64(MCH_SSKPD);

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