Commit 06f976ec authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux 

Pull arm64 fixes from Will Deacon:
 "There are some significant fixes in here for FP state corruption,
  hardware access/dirty PTE corruption and an erratum workaround for the
  Falkor CPU.

  I'm hoping that things finally settle down now, but never say never...

  Summary:

   - Fix FPSIMD context switch regression introduced in -rc2

   - Fix ABI break with SVE CPUID register reporting

   - Fix use of uninitialised variable

   - Fixes to hardware access/dirty management and sanity checking

   - CPU erratum workaround for Falkor CPUs

   - Fix reporting of writeable+executable mappings

   - Fix signal reporting for RAS errors"

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64: fpsimd: Fix copying of FP state from signal frame into task struct
  arm64/sve: Report SVE to userspace via CPUID only if supported
  arm64: fix CONFIG_DEBUG_WX address reporting
  arm64: fault: avoid send SIGBUS two times
  arm64: hw_breakpoint: Use linux/uaccess.h instead of asm/uaccess.h
  arm64: Add software workaround for Falkor erratum 1041
  arm64: Define cputype macros for Falkor CPU
  arm64: mm: Fix false positives in set_pte_at access/dirty race detection
  arm64: mm: Fix pte_mkclean, pte_mkdirty semantics
  arm64: Initialise high_memory global variable earlier
parents e53000b1 a4544831

Documentation/arm64/silicon-errata.txt

+1 −0
Original line number Diff line number Diff line
@@ -75,3 +75,4 @@ stable kernels. 
| Qualcomm Tech. | Falkor v1       | E1003           | QCOM_FALKOR_ERRATUM_1003    |

| Qualcomm Tech. | Falkor v1       | E1009           | QCOM_FALKOR_ERRATUM_1009    |

| Qualcomm Tech. | QDF2400 ITS     | E0065           | QCOM_QDF2400_ERRATUM_0065   |

| Qualcomm Tech. | Falkor v{1,2}   | E1041           | QCOM_FALKOR_ERRATUM_1041    |

arch/arm64/Kconfig

+11 −1
Original line number Diff line number Diff line
@@ -557,7 +557,6 @@ config QCOM_QDF2400_ERRATUM_0065 


	  If unsure, say Y.





config SOCIONEXT_SYNQUACER_PREITS

	bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"

	default y
@@ -576,6 +575,17 @@ config HISILICON_ERRATUM_161600802 
	  a 128kB offset to be applied to the target address in this commands.



	  If unsure, say Y.



config QCOM_FALKOR_ERRATUM_E1041

	bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"

	default y

	help

	  Falkor CPU may speculatively fetch instructions from an improper

	  memory location when MMU translation is changed from SCTLR_ELn[M]=1

	  to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.



	  If unsure, say Y.



endmenu

arch/arm64/include/asm/assembler.h

+10 −0
Original line number Diff line number Diff line
@@ -512,4 +512,14 @@ alternative_else_nop_endif 
#endif

	.endm



/**

 * Errata workaround prior to disable MMU. Insert an ISB immediately prior

 * to executing the MSR that will change SCTLR_ELn[M] from a value of 1 to 0.

 */

	.macro pre_disable_mmu_workaround

#ifdef CONFIG_QCOM_FALKOR_ERRATUM_E1041

	isb

#endif

	.endm



#endif	/* __ASM_ASSEMBLER_H */

arch/arm64/include/asm/cpufeature.h

+3 −0
Original line number Diff line number Diff line
@@ -60,6 +60,9 @@ enum ftr_type { 
#define FTR_VISIBLE	true	/* Feature visible to the user space */

#define FTR_HIDDEN	false	/* Feature is hidden from the user */



#define FTR_VISIBLE_IF_IS_ENABLED(config)		\

	(IS_ENABLED(config) ? FTR_VISIBLE : FTR_HIDDEN)



struct arm64_ftr_bits {

	bool		sign;	/* Value is signed ? */

	bool		visible;

arch/arm64/include/asm/cputype.h

+2 −0
Original line number Diff line number Diff line
@@ -91,6 +91,7 @@ 
#define BRCM_CPU_PART_VULCAN		0x516



#define QCOM_CPU_PART_FALKOR_V1		0x800

#define QCOM_CPU_PART_FALKOR		0xC00



#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)

#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
@@ -99,6 +100,7 @@ 
#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)

#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)

#define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)

#define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR)



#ifndef __ASSEMBLY__

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