Commit 06f31cb0 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge branch 'vexpress-clk-soc' of git://git.linaro.org/people/pawelmoll/linux into next/soc 

From Pawel Moll:
* 'vexpress-clk-soc' of git://git.linaro.org/people/pawelmoll/linux:
  ARM: vexpress: Remove motherboard dependencies in the DTS files
  ARM: vexpress: Start using new Versatile Express infrastructure
  ARM: vexpress: Add config bus components and clocks to DTs
  mfd: Versatile Express system registers driver
  mfd: Versatile Express config infrastructure
parents 17bffc78 433683a6

Documentation/devicetree/bindings/arm/vexpress-sysreg.txt

0 → 100644
+50 −0
Original line number Diff line number Diff line 
ARM Versatile Express system registers

--------------------------------------



This is a system control registers block, providing multiple low level

platform functions like board detection and identification, software

interrupt generation, MMC and NOR Flash control etc.



Required node properties:

- compatible value : = "arm,vexpress,sysreg";

- reg : physical base address and the size of the registers window

- gpio-controller : specifies that the node is a GPIO controller

- #gpio-cells : size of the GPIO specifier, should be 2:

  - first cell is the pseudo-GPIO line number:

    0 - MMC CARDIN

    1 - MMC WPROT

    2 - NOR FLASH WPn

  - second cell can take standard GPIO flags (currently ignored).



Example:

	v2m_sysreg: sysreg@10000000 {

 		compatible = "arm,vexpress-sysreg";

 		reg = <0x10000000 0x1000>;

		gpio-controller;

		#gpio-cells = <2>;

 	};



This block also can also act a bridge to the platform's configuration

bus via "system control" interface, addressing devices with site number,

position in the board stack, config controller, function and device

numbers - see motherboard's TRM for more details.



The node describing a config device must refer to the sysreg node via

"arm,vexpress,config-bridge" phandle (can be also defined in the node's

parent) and relies on the board topology properties - see main vexpress

node documentation for more details. It must must also define the

following property:

- arm,vexpress-sysreg,func : must contain two cells:

  - first cell defines function number (eg. 1 for clock generator,

    2 for voltage regulators etc.)

  - device number (eg. osc 0, osc 1 etc.)



Example:

	mcc {

		arm,vexpress,config-bridge = <&v2m_sysreg>;



		osc@0 {

			compatible = "arm,vexpress-osc";

			arm,vexpress-sysreg,func = <1 0>;

		};

	};

Documentation/devicetree/bindings/arm/vexpress.txt

+88 −10
Original line number Diff line number Diff line
@@ -11,6 +11,10 @@ the motherboard file using a /include/ directive. As the motherboard 
can be initialized in one of two different configurations ("memory

maps"), care must be taken to include the correct one.





Root node

---------



Required properties in the root node:

- compatible value:

	compatible = "arm,vexpress,<model>", "arm,vexpress";
@@ -45,6 +49,10 @@ Optional properties in the root node: 
  - Coretile Express A9x4 (V2P-CA9) HBI-0225:

	arm,hbi = <0x225>;





CPU nodes

---------



Top-level standard "cpus" node is required. It must contain a node

with device_type = "cpu" property for every available core, eg.:
@@ -59,6 +67,52 @@ with device_type = "cpu" property for every available core, eg.: 
		};

	};





Configuration infrastructure

----------------------------



The platform has an elaborated configuration system, consisting of

microcontrollers residing on the mother- and daughterboards known

as Motherboard/Daughterboard Configuration Controller (MCC and DCC).

The controllers are responsible for the platform initialization

(reset generation, flash programming, FPGA bitfiles loading etc.)

but also control clock generators, voltage regulators, gather

environmental data like temperature, power consumption etc. Even

the video output switch (FPGA) is controlled that way.



Nodes describing devices controlled by this infrastructure should

point at the bridge device node:

- bridge phandle:

	arm,vexpress,config-bridge = <phandle>;

This property can be also defined in a parent node (eg. for a DCC)

and is effective for all children.





Platform topology

-----------------



As Versatile Express can be configured in number of physically

different setups, the device tree should describe platform topology.

Root node and main motherboard node must define the following

property, describing physical location of the children nodes:

- site number:

	arm,vexpress,site = <number>;

  where 0 means motherboard, 1 or 2 are daugtherboard sites,

  0xf means "master" site (site containing main CPU tile)

- when daughterboards are stacked on one site, their position

  in the stack be be described with:

	arm,vexpress,position = <number>;

- when describing tiles consisting more than one DCC, its number

  can be described with:

	arm,vexpress,dcc = <number>;



Any of the numbers above defaults to zero if not defined in

the node or any of its parent.





Motherboard

-----------



The motherboard description file provides a single "motherboard" node

using 2 address cells corresponding to the Static Memory Bus used

between the motherboard and the tile. The first cell defines the Chip
@@ -87,22 +141,30 @@ can be used to obtain required phandle in the tile's "aliases" node: 
- SP804 timers:

	v2m_timer01 and v2m_timer23



Current Linux implementation requires a "arm,v2m_timer" alias

pointing at one of the motherboard's SP804 timers, if it is to be

used as the system timer. This alias should be defined in the

motherboard files.

The tile description should define a "smb" node, describing the

Static Memory Bus between the tile and motherboard. It must define

the following properties:

- "simple-bus" compatible value (to ensure creation of the children)

	compatible = "simple-bus";

- mapping of the SMB CS/offset addresses into main address space:

	#address-cells = <2>;

	#size-cells = <1>;

	ranges = <...>;

- interrupts mapping:

	#interrupt-cells = <1>;

	interrupt-map-mask = <0 0 63>;

	interrupt-map = <...>;



The tile description must define "ranges", "interrupt-map-mask" and

"interrupt-map" properties to translate the motherboard's address

and interrupt space into one used by the tile's processor.



Abbreviated example:

Example of a VE tile description (simplified)

---------------------------------------------



/dts-v1/;



/ {

	model = "V2P-CA5s";

	arm,hbi = <0x225>;

	arm,vexpress,site = <0xf>;

	compatible = "arm,vexpress-v2p-ca5s", "arm,vexpress";

	interrupt-parent = <&gic>;

	#address-cells = <1>;
@@ -134,13 +196,29 @@ Abbreviated example: 
		      <0x2c000100 0x100>;

	};



	motherboard {

	dcc {

		compatible = "simple-bus";

		arm,vexpress,config-bridge = <&v2m_sysreg>;



		osc@0 {

			compatible = "arm,vexpress-osc";

		};

	};



	smb {

		compatible = "simple-bus";



		#address-cells = <2>;

		#size-cells = <1>;

		/* CS0 is visible at 0x08000000 */

		ranges = <0 0 0x08000000 0x04000000>;



		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 63>;

		/* Active high IRQ 0 is connected to GIC's SPI0 */

		interrupt-map = <0 0 0 &gic 0 0 4>;



		/include/ "vexpress-v2m-rs1.dtsi"

	};

};

/include/ "vexpress-v2m-rs1.dtsi"

arch/arm/boot/dts/vexpress-v2m-rs1.dtsi

+137 −9
Original line number Diff line number Diff line
@@ -17,17 +17,16 @@ 
 * CHANGES TO vexpress-v2m.dtsi!

 */



/ {

	aliases {

		arm,v2m_timer = &v2m_timer01;

	};



	motherboard {

		compatible = "simple-bus";

		model = "V2M-P1";

		arm,hbi = <0x190>;

		arm,vexpress,site = <0>;

		arm,v2m-memory-map = "rs1";

		compatible = "arm,vexpress,v2m-p1", "simple-bus";

		#address-cells = <2>; /* SMB chipselect number and offset */

		#size-cells = <1>;

		#interrupt-cells = <1>;

		ranges;



		flash@0,00000000 {

			compatible = "arm,vexpress-flash", "cfi-flash";
@@ -72,14 +71,20 @@ 
			#size-cells = <1>;

			ranges = <0 3 0 0x200000>;



			sysreg@010000 {

			v2m_sysreg: sysreg@010000 {

				compatible = "arm,vexpress-sysreg";

				reg = <0x010000 0x1000>;

				gpio-controller;

				#gpio-cells = <2>;

			};



			sysctl@020000 {

			v2m_sysctl: sysctl@020000 {

				compatible = "arm,sp810", "arm,primecell";

				reg = <0x020000 0x1000>;

				clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;

				clock-names = "refclk", "timclk", "apb_pclk";

				#clock-cells = <1>;

				clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";

			};



			/* PCI-E I2C bus */
@@ -100,66 +105,92 @@ 
				compatible = "arm,pl041", "arm,primecell";

				reg = <0x040000 0x1000>;

				interrupts = <11>;

				clocks = <&smbclk>;

				clock-names = "apb_pclk";

			};



			mmci@050000 {

				compatible = "arm,pl180", "arm,primecell";

				reg = <0x050000 0x1000>;

				interrupts = <9 10>;

				cd-gpios = <&v2m_sysreg 0 0>;

				wp-gpios = <&v2m_sysreg 1 0>;

				max-frequency = <12000000>;

				vmmc-supply = <&v2m_fixed_3v3>;

				clocks = <&v2m_clk24mhz>, <&smbclk>;

				clock-names = "mclk", "apb_pclk";

			};



			kmi@060000 {

				compatible = "arm,pl050", "arm,primecell";

				reg = <0x060000 0x1000>;

				interrupts = <12>;

				clocks = <&v2m_clk24mhz>, <&smbclk>;

				clock-names = "KMIREFCLK", "apb_pclk";

			};



			kmi@070000 {

				compatible = "arm,pl050", "arm,primecell";

				reg = <0x070000 0x1000>;

				interrupts = <13>;

				clocks = <&v2m_clk24mhz>, <&smbclk>;

				clock-names = "KMIREFCLK", "apb_pclk";

			};



			v2m_serial0: uart@090000 {

				compatible = "arm,pl011", "arm,primecell";

				reg = <0x090000 0x1000>;

				interrupts = <5>;

				clocks = <&v2m_oscclk2>, <&smbclk>;

				clock-names = "uartclk", "apb_pclk";

			};



			v2m_serial1: uart@0a0000 {

				compatible = "arm,pl011", "arm,primecell";

				reg = <0x0a0000 0x1000>;

				interrupts = <6>;

				clocks = <&v2m_oscclk2>, <&smbclk>;

				clock-names = "uartclk", "apb_pclk";

			};



			v2m_serial2: uart@0b0000 {

				compatible = "arm,pl011", "arm,primecell";

				reg = <0x0b0000 0x1000>;

				interrupts = <7>;

				clocks = <&v2m_oscclk2>, <&smbclk>;

				clock-names = "uartclk", "apb_pclk";

			};



			v2m_serial3: uart@0c0000 {

				compatible = "arm,pl011", "arm,primecell";

				reg = <0x0c0000 0x1000>;

				interrupts = <8>;

				clocks = <&v2m_oscclk2>, <&smbclk>;

				clock-names = "uartclk", "apb_pclk";

			};



			wdt@0f0000 {

				compatible = "arm,sp805", "arm,primecell";

				reg = <0x0f0000 0x1000>;

				interrupts = <0>;

				clocks = <&v2m_refclk32khz>, <&smbclk>;

				clock-names = "wdogclk", "apb_pclk";

			};



			v2m_timer01: timer@110000 {

				compatible = "arm,sp804", "arm,primecell";

				reg = <0x110000 0x1000>;

				interrupts = <2>;

				clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;

				clock-names = "timclken1", "timclken2", "apb_pclk";

			};



			v2m_timer23: timer@120000 {

				compatible = "arm,sp804", "arm,primecell";

				reg = <0x120000 0x1000>;

				interrupts = <3>;

				clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;

				clock-names = "timclken1", "timclken2", "apb_pclk";

			};



			/* DVI I2C bus */
@@ -185,6 +216,8 @@ 
				compatible = "arm,pl031", "arm,primecell";

				reg = <0x170000 0x1000>;

				interrupts = <4>;

				clocks = <&smbclk>;

				clock-names = "apb_pclk";

			};



			compact-flash@1a0000 {
@@ -198,6 +231,8 @@ 
				compatible = "arm,pl111", "arm,primecell";

				reg = <0x1f0000 0x1000>;

				interrupts = <14>;

				clocks = <&v2m_oscclk1>, <&smbclk>;

				clock-names = "clcdclk", "apb_pclk";

			};

		};
@@ -208,5 +243,98 @@ 
			regulator-max-microvolt = <3300000>;

			regulator-always-on;

		};



		v2m_clk24mhz: clk24mhz {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <24000000>;

			clock-output-names = "v2m:clk24mhz";

		};



		v2m_refclk1mhz: refclk1mhz {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <1000000>;

			clock-output-names = "v2m:refclk1mhz";

		};



		v2m_refclk32khz: refclk32khz {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <32768>;

			clock-output-names = "v2m:refclk32khz";

		};



		mcc {

			compatible = "arm,vexpress,config-bus";

			arm,vexpress,config-bridge = <&v2m_sysreg>;



			osc@0 {

				/* MCC static memory clock */

				compatible = "arm,vexpress-osc";

				arm,vexpress-sysreg,func = <1 0>;

				freq-range = <25000000 60000000>;

				#clock-cells = <0>;

				clock-output-names = "v2m:oscclk0";

			};



			v2m_oscclk1: osc@1 {

				/* CLCD clock */

				compatible = "arm,vexpress-osc";

				arm,vexpress-sysreg,func = <1 1>;

				freq-range = <23750000 63500000>;

				#clock-cells = <0>;

				clock-output-names = "v2m:oscclk1";

			};



			v2m_oscclk2: osc@2 {

				/* IO FPGA peripheral clock */

				compatible = "arm,vexpress-osc";

				arm,vexpress-sysreg,func = <1 2>;

				freq-range = <24000000 24000000>;

				#clock-cells = <0>;

				clock-output-names = "v2m:oscclk2";

			};



			volt@0 {

				/* Logic level voltage */

				compatible = "arm,vexpress-volt";

				arm,vexpress-sysreg,func = <2 0>;

				regulator-name = "VIO";

				regulator-always-on;

				label = "VIO";

			};



			temp@0 {

				/* MCC internal operating temperature */

				compatible = "arm,vexpress-temp";

				arm,vexpress-sysreg,func = <4 0>;

				label = "MCC";

			};



			reset@0 {

				compatible = "arm,vexpress-reset";

				arm,vexpress-sysreg,func = <5 0>;

			};



			muxfpga@0 {

				compatible = "arm,vexpress-muxfpga";

				arm,vexpress-sysreg,func = <7 0>;

			};



			shutdown@0 {

				compatible = "arm,vexpress-shutdown";

				arm,vexpress-sysreg,func = <8 0>;

			};



			reboot@0 {

				compatible = "arm,vexpress-reboot";

				arm,vexpress-sysreg,func = <9 0>;

			};



			dvimode@0 {

				compatible = "arm,vexpress-dvimode";

				arm,vexpress-sysreg,func = <11 0>;

			};

		};

	};

arch/arm/boot/dts/vexpress-v2m.dtsi

+137 −9
Original line number Diff line number Diff line
@@ -17,16 +17,15 @@ 
 * CHANGES TO vexpress-v2m-rs1.dtsi!

 */



/ {

	aliases {

		arm,v2m_timer = &v2m_timer01;

	};



	motherboard {

		compatible = "simple-bus";

		model = "V2M-P1";

		arm,hbi = <0x190>;

		arm,vexpress,site = <0>;

		compatible = "arm,vexpress,v2m-p1", "simple-bus";

		#address-cells = <2>; /* SMB chipselect number and offset */

		#size-cells = <1>;

		#interrupt-cells = <1>;

		ranges;



		flash@0,00000000 {

			compatible = "arm,vexpress-flash", "cfi-flash";
@@ -71,14 +70,20 @@ 
			#size-cells = <1>;

			ranges = <0 7 0 0x20000>;



			sysreg@00000 {

			v2m_sysreg: sysreg@00000 {

				compatible = "arm,vexpress-sysreg";

				reg = <0x00000 0x1000>;

				gpio-controller;

				#gpio-cells = <2>;

			};



			sysctl@01000 {

			v2m_sysctl: sysctl@01000 {

				compatible = "arm,sp810", "arm,primecell";

				reg = <0x01000 0x1000>;

				clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;

				clock-names = "refclk", "timclk", "apb_pclk";

				#clock-cells = <1>;

				clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";

			};



			/* PCI-E I2C bus */
@@ -99,66 +104,92 @@ 
				compatible = "arm,pl041", "arm,primecell";

				reg = <0x04000 0x1000>;

				interrupts = <11>;

				clocks = <&smbclk>;

				clock-names = "apb_pclk";

			};



			mmci@05000 {

				compatible = "arm,pl180", "arm,primecell";

				reg = <0x05000 0x1000>;

				interrupts = <9 10>;

				cd-gpios = <&v2m_sysreg 0 0>;

				wp-gpios = <&v2m_sysreg 1 0>;

				max-frequency = <12000000>;

				vmmc-supply = <&v2m_fixed_3v3>;

				clocks = <&v2m_clk24mhz>, <&smbclk>;

				clock-names = "mclk", "apb_pclk";

			};



			kmi@06000 {

				compatible = "arm,pl050", "arm,primecell";

				reg = <0x06000 0x1000>;

				interrupts = <12>;

				clocks = <&v2m_clk24mhz>, <&smbclk>;

				clock-names = "KMIREFCLK", "apb_pclk";

			};



			kmi@07000 {

				compatible = "arm,pl050", "arm,primecell";

				reg = <0x07000 0x1000>;

				interrupts = <13>;

				clocks = <&v2m_clk24mhz>, <&smbclk>;

				clock-names = "KMIREFCLK", "apb_pclk";

			};



			v2m_serial0: uart@09000 {

				compatible = "arm,pl011", "arm,primecell";

				reg = <0x09000 0x1000>;

				interrupts = <5>;

				clocks = <&v2m_oscclk2>, <&smbclk>;

				clock-names = "uartclk", "apb_pclk";

			};



			v2m_serial1: uart@0a000 {

				compatible = "arm,pl011", "arm,primecell";

				reg = <0x0a000 0x1000>;

				interrupts = <6>;

				clocks = <&v2m_oscclk2>, <&smbclk>;

				clock-names = "uartclk", "apb_pclk";

			};



			v2m_serial2: uart@0b000 {

				compatible = "arm,pl011", "arm,primecell";

				reg = <0x0b000 0x1000>;

				interrupts = <7>;

				clocks = <&v2m_oscclk2>, <&smbclk>;

				clock-names = "uartclk", "apb_pclk";

			};



			v2m_serial3: uart@0c000 {

				compatible = "arm,pl011", "arm,primecell";

				reg = <0x0c000 0x1000>;

				interrupts = <8>;

				clocks = <&v2m_oscclk2>, <&smbclk>;

				clock-names = "uartclk", "apb_pclk";

			};



			wdt@0f000 {

				compatible = "arm,sp805", "arm,primecell";

				reg = <0x0f000 0x1000>;

				interrupts = <0>;

				clocks = <&v2m_refclk32khz>, <&smbclk>;

				clock-names = "wdogclk", "apb_pclk";

			};



			v2m_timer01: timer@11000 {

				compatible = "arm,sp804", "arm,primecell";

				reg = <0x11000 0x1000>;

				interrupts = <2>;

				clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;

				clock-names = "timclken1", "timclken2", "apb_pclk";

			};



			v2m_timer23: timer@12000 {

				compatible = "arm,sp804", "arm,primecell";

				reg = <0x12000 0x1000>;

				interrupts = <3>;

				clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;

				clock-names = "timclken1", "timclken2", "apb_pclk";

			};



			/* DVI I2C bus */
@@ -184,6 +215,8 @@ 
				compatible = "arm,pl031", "arm,primecell";

				reg = <0x17000 0x1000>;

				interrupts = <4>;

				clocks = <&smbclk>;

				clock-names = "apb_pclk";

			};



			compact-flash@1a000 {
@@ -197,6 +230,8 @@ 
				compatible = "arm,pl111", "arm,primecell";

				reg = <0x1f000 0x1000>;

				interrupts = <14>;

				clocks = <&v2m_oscclk1>, <&smbclk>;

				clock-names = "clcdclk", "apb_pclk";

			};

		};
@@ -207,5 +242,98 @@ 
			regulator-max-microvolt = <3300000>;

			regulator-always-on;

		};



		v2m_clk24mhz: clk24mhz {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <24000000>;

			clock-output-names = "v2m:clk24mhz";

		};



		v2m_refclk1mhz: refclk1mhz {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <1000000>;

			clock-output-names = "v2m:refclk1mhz";

		};



		v2m_refclk32khz: refclk32khz {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <32768>;

			clock-output-names = "v2m:refclk32khz";

		};



		mcc {

			compatible = "arm,vexpress,config-bus";

			arm,vexpress,config-bridge = <&v2m_sysreg>;



			osc@0 {

				/* MCC static memory clock */

				compatible = "arm,vexpress-osc";

				arm,vexpress-sysreg,func = <1 0>;

				freq-range = <25000000 60000000>;

				#clock-cells = <0>;

				clock-output-names = "v2m:oscclk0";

			};



			v2m_oscclk1: osc@1 {

				/* CLCD clock */

				compatible = "arm,vexpress-osc";

				arm,vexpress-sysreg,func = <1 1>;

				freq-range = <23750000 63500000>;

				#clock-cells = <0>;

				clock-output-names = "v2m:oscclk1";

			};



			v2m_oscclk2: osc@2 {

				/* IO FPGA peripheral clock */

				compatible = "arm,vexpress-osc";

				arm,vexpress-sysreg,func = <1 2>;

				freq-range = <24000000 24000000>;

				#clock-cells = <0>;

				clock-output-names = "v2m:oscclk2";

			};



			volt@0 {

				/* Logic level voltage */

				compatible = "arm,vexpress-volt";

				arm,vexpress-sysreg,func = <2 0>;

				regulator-name = "VIO";

				regulator-always-on;

				label = "VIO";

			};



			temp@0 {

				/* MCC internal operating temperature */

				compatible = "arm,vexpress-temp";

				arm,vexpress-sysreg,func = <4 0>;

				label = "MCC";

			};



			reset@0 {

				compatible = "arm,vexpress-reset";

				arm,vexpress-sysreg,func = <5 0>;

			};



			muxfpga@0 {

				compatible = "arm,vexpress-muxfpga";

				arm,vexpress-sysreg,func = <7 0>;

			};



			shutdown@0 {

				compatible = "arm,vexpress-shutdown";

				arm,vexpress-sysreg,func = <8 0>;

			};



			reboot@0 {

				compatible = "arm,vexpress-reboot";

				arm,vexpress-sysreg,func = <9 0>;

			};



			dvimode@0 {

				compatible = "arm,vexpress-dvimode";

				arm,vexpress-sysreg,func = <11 0>;

			};

		};

	};

arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts

+118 −3
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 
/ {

	model = "V2P-CA15";

	arm,hbi = <0x237>;

	arm,vexpress,site = <0xf>;

	compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";

	interrupt-parent = <&gic>;

	#address-cells = <2>;
@@ -54,17 +55,24 @@ 
		compatible = "arm,hdlcd";

		reg = <0 0x2b000000 0 0x1000>;

		interrupts = <0 85 4>;

		clocks = <&oscclk5>;

		clock-names = "pxlclk";

	};



	memory-controller@2b0a0000 {

		compatible = "arm,pl341", "arm,primecell";

		reg = <0 0x2b0a0000 0 0x1000>;

		clocks = <&oscclk7>;

		clock-names = "apb_pclk";

	};



	wdt@2b060000 {

		compatible = "arm,sp805", "arm,primecell";

		status = "disabled";

		reg = <0 0x2b060000 0 0x1000>;

		interrupts = <98>;

		clocks = <&oscclk7>;

		clock-names = "apb_pclk";

	};



	gic: interrupt-controller@2c001000 {
@@ -84,6 +92,8 @@ 
		reg = <0 0x7ffd0000 0 0x1000>;

		interrupts = <0 86 4>,

			     <0 87 4>;

		clocks = <&oscclk7>;

		clock-names = "apb_pclk";

	};



	dma@7ffb0000 {
@@ -94,6 +104,8 @@ 
			     <0 89 4>,

			     <0 90 4>,

			     <0 91 4>;

		clocks = <&oscclk7>;

		clock-names = "apb_pclk";

	};



	timer {
@@ -110,7 +122,109 @@ 
			     <0 69 4>;

	};



	motherboard {

	dcc {

		compatible = "arm,vexpress,config-bus";

		arm,vexpress,config-bridge = <&v2m_sysreg>;



		osc@0 {

			/* CPU PLL reference clock */

			compatible = "arm,vexpress-osc";

			arm,vexpress-sysreg,func = <1 0>;

			freq-range = <50000000 60000000>;

			#clock-cells = <0>;

			clock-output-names = "oscclk0";

		};



		osc@4 {

			/* Multiplexed AXI master clock */

			compatible = "arm,vexpress-osc";

			arm,vexpress-sysreg,func = <1 4>;

			freq-range = <20000000 40000000>;

			#clock-cells = <0>;

			clock-output-names = "oscclk4";

		};



		oscclk5: osc@5 {

			/* HDLCD PLL reference clock */

			compatible = "arm,vexpress-osc";

			arm,vexpress-sysreg,func = <1 5>;

			freq-range = <23750000 165000000>;

			#clock-cells = <0>;

			clock-output-names = "oscclk5";

		};



		smbclk: osc@6 {

			/* SMB clock */

			compatible = "arm,vexpress-osc";

			arm,vexpress-sysreg,func = <1 6>;

			freq-range = <20000000 50000000>;

			#clock-cells = <0>;

			clock-output-names = "oscclk6";

		};



		oscclk7: osc@7 {

			/* SYS PLL reference clock */

			compatible = "arm,vexpress-osc";

			arm,vexpress-sysreg,func = <1 7>;

			freq-range = <20000000 60000000>;

			#clock-cells = <0>;

			clock-output-names = "oscclk7";

		};



		osc@8 {

			/* DDR2 PLL reference clock */

			compatible = "arm,vexpress-osc";

			arm,vexpress-sysreg,func = <1 8>;

			freq-range = <40000000 40000000>;

			#clock-cells = <0>;

			clock-output-names = "oscclk8";

		};



		volt@0 {

			/* CPU core voltage */

			compatible = "arm,vexpress-volt";

			arm,vexpress-sysreg,func = <2 0>;

			regulator-name = "Cores";

			regulator-min-microvolt = <800000>;

			regulator-max-microvolt = <1050000>;

			regulator-always-on;

			label = "Cores";

		};



		amp@0 {

			/* Total current for the two cores */

			compatible = "arm,vexpress-amp";

			arm,vexpress-sysreg,func = <3 0>;

			label = "Cores";

		};



		temp@0 {

			/* DCC internal temperature */

			compatible = "arm,vexpress-temp";

			arm,vexpress-sysreg,func = <4 0>;

			label = "DCC";

		};



		power@0 {

			/* Total power */

			compatible = "arm,vexpress-power";

			arm,vexpress-sysreg,func = <12 0>;

			label = "Cores";

		};



		energy@0 {

			/* Total energy */

			compatible = "arm,vexpress-energy";

			arm,vexpress-sysreg,func = <13 0>;

			label = "Cores";

		};

	};



	smb {

		compatible = "simple-bus";



		#address-cells = <2>;

		#size-cells = <1>;

		ranges = <0 0 0 0x08000000 0x04000000>,

			 <1 0 0 0x14000000 0x04000000>,

			 <2 0 0 0x18000000 0x04000000>,
@@ -118,6 +232,7 @@ 
			 <4 0 0 0x0c000000 0x04000000>,

			 <5 0 0 0x10000000 0x04000000>;



		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 63>;

		interrupt-map = <0 0  0 &gic 0  0 4>,

				<0 0  1 &gic 0  1 4>,
@@ -162,7 +277,7 @@ 
				<0 0 40 &gic 0 40 4>,

				<0 0 41 &gic 0 41 4>,

				<0 0 42 &gic 0 42 4>;

	};

};



		/include/ "vexpress-v2m-rs1.dtsi"

	};

};

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