Commit 06dd94cc authored Mar 14, 2019 by José Roberto de Souza

drm/i915: Fix PSR2 selective update corruption after PSR1 setup



There is probably a issue in DMC firmwares(icl_dmc_ver1_07.bin and
kbl_dmc_ver1_04.bin at least) that causes PSR2 SU to fail after
exiting DC6 if EDP_PSR_TP1_TP3_SEL is kept in PSR_CTL, so for now
lets workaround the issue by cleaning PSR_CTL before enable PSR2.

v2:
- Updated commit description and comment to state that it may be
a DMC firmware issue (Rodrigo)
- No need to RMW, let's write 0 to PSR_CTL(Dhinakaran)

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190314230113.6571-1-jose.souza@intel.com

parent d2daff2c

drivers/gpu/drm/i915/intel_psr.c

+8 −0

Original line number	Original line	Diff line number	Diff line
	@@ -530,6 +530,14 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
	else		else
	val \|= EDP_PSR2_TP2_TIME_2500us;		val \|= EDP_PSR2_TP2_TIME_2500us;

			/*
			* FIXME: There is probably a issue in DMC firmwares(icl_dmc_ver1_07.bin
			* and kbl_dmc_ver1_04.bin at least) that causes PSR2 SU to fail after
			* exiting DC6 if EDP_PSR_TP1_TP3_SEL is kept in PSR_CTL, so for now
			* lets workaround the issue by cleaning PSR_CTL before enable PSR2.
			*/
			I915_WRITE(EDP_PSR_CTL, 0);

	I915_WRITE(EDP_PSR2_CTL, val);		I915_WRITE(EDP_PSR2_CTL, val);
	}		}

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