Commit 06dcd7eb authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: check GFX RAS capability before reset counters 



disallow the logical to be enabled on platforms that
don't support gfx ras at this stage, like sriov skus,
dgpu with legacy ras.etc

Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarMonk Liu <monk.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c2c6f816

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+3 −0
Original line number Diff line number Diff line
@@ -6306,6 +6306,9 @@ static void gfx_v9_0_reset_ras_error_count(struct amdgpu_device *adev) 
{

	int i, j, k;



	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))

		return;



	/* read back registers to clear the counters */

	mutex_lock(&adev->grbm_idx_mutex);

	for (i = 0; i < ARRAY_SIZE(gfx_v9_0_edc_counter_regs); i++) {

drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c

+3 −0
Original line number Diff line number Diff line
@@ -897,6 +897,9 @@ void gfx_v9_4_reset_ras_error_count(struct amdgpu_device *adev) 
{

	int i, j, k;



	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))

		return;



	mutex_lock(&adev->grbm_idx_mutex);

	for (i = 0; i < ARRAY_SIZE(gfx_v9_4_edc_counter_regs); i++) {

		for (j = 0; j < gfx_v9_4_edc_counter_regs[i].se_num; j++) {

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