Commit 06cc5c1d authored by Haifeng Yan's avatar Haifeng Yan Committed by Olof Johansson
Browse files

ARM: hisi: enable hix5hd2 SoC 



Enable support for the Hisilicon HiX5HD2 SoC. This HiX5HD2 SoC series
support both single and dual Cortex-A9 cores.

Add ARCH_HIX5HD2 to distinguish HiX5HD2 from Hi3xxx.

They are different in implementation such as SMP, IPs integarted and
earlycon configure.

Signed-off-by: default avatarHaifeng Yan <yanhaifeng@gmail.com>
Signed-off-by: default avatarJiancheng Xue <jchxue@gmail.com>
Signed-off-by: default avatarHaojian Zhuang <haojian.zhuang@linaro.org>
Acked-by: default avatarWei Xu <xuwei5@hisilicon.com>
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parent 7685b125

Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt

+11 −0
Original line number Diff line number Diff line
@@ -31,6 +31,17 @@ Example: 
		reboot-offset = <0x4>;

	};



-----------------------------------------------------------------------

Hisilicon CPU controller



Required properties:

- compatible : "hisilicon,cpuctrl"

- reg : Register address and size



The clock registers and power registers of secondary cores are defined

in CPU controller, especially in HIX5HD2 SoC.



-----------------------------------------------------------------------

PCTRL: Peripheral misc control register



Required Properties:

arch/arm/mach-hisi/Kconfig

+11 −2
Original line number Diff line number Diff line
@@ -10,15 +10,24 @@ if ARCH_HISI 
menu "Hisilicon platform type"



config ARCH_HI3xxx

	bool "Hisilicon Hi36xx/Hi37xx family" if ARCH_MULTI_V7

	bool "Hisilicon Hi36xx family" if ARCH_MULTI_V7

	select CACHE_L2X0

	select HAVE_ARM_SCU if SMP

	select HAVE_ARM_TWD if SMP

	select PINCTRL

	select PINCTRL_SINGLE

	help

	  Support for Hisilicon Hi36xx/Hi37xx processor family

	  Support for Hisilicon Hi36xx SoC family



config ARCH_HIX5HD2

	bool "Hisilicon X5HD2 family" if ARCH_MULTI_V7

	select CACHE_L2X0

	select HAVE_ARM_SCU if SMP

	select HAVE_ARM_TWD if SMP

	select PINCTRL

	select PINCTRL_SINGLE

	help

	  Support for Hisilicon HIX5HD2 SoC family

endmenu



endif

arch/arm/mach-hisi/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -3,4 +3,4 @@ 
#



obj-y	+= hisilicon.o

obj-$(CONFIG_SMP)		+= platsmp.o hotplug.o
 
obj-$(CONFIG_SMP)		+= platsmp.o hotplug.o headsmp.o

arch/arm/mach-hisi/core.h

+5 −0
Original line number Diff line number Diff line
@@ -12,4 +12,9 @@ extern void hi3xxx_cpu_die(unsigned int cpu); 
extern int hi3xxx_cpu_kill(unsigned int cpu);

extern void hi3xxx_set_cpu(int cpu, bool enable);



extern void hix5hd2_secondary_startup(void);

extern struct smp_operations hix5hd2_smp_ops;

extern void hix5hd2_set_cpu(int cpu, bool enable);

extern void hix5hd2_cpu_die(unsigned int cpu);



#endif

arch/arm/mach-hisi/headsmp.S

0 → 100644
+16 −0
Original line number Diff line number Diff line 
/*

 *  Copyright (c) 2014 Hisilicon Limited.

 *  Copyright (c) 2014 Linaro Ltd.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */

#include <linux/linkage.h>

#include <linux/init.h>



	__CPUINIT



ENTRY(hix5hd2_secondary_startup)

	bl	v7_invalidate_l1

	b	secondary_startup

CRA Git | Maintained and supported by SUSTech CRA and CCSE