Commit 06c7a489 authored Oct 07, 2010 by Paul Mundt

sh: Fix up the SH-3 build.



SH-3 lacks an MMUCR_TI definition for global TLB flushes. As SH-3 parts
lack a split TLB, the same global flush behaviour is accomplished
through the flush bit, which just happens to be the same as on SH-4.

This fixes up the build for all SH-3 MMU parts.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

parent 901c28c2

arch/sh/include/cpu-sh3/cpu/mmu_context.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -16,6 +16,7 @@
		#define MMU_TEA 0xFFFFFFFC /* TLB Exception Address */

		#define MMUCR 0xFFFFFFE0 /* MMU Control Register */
		#define MMUCR_TI (1 << 2) /* TLB flush bit */

		#define MMU_TLB_ADDRESS_ARRAY 0xF2000000
		#define MMU_PAGE_ASSOC_BIT 0x80

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