Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc

could race with data DMA.  Mapping the memory used for completion

indications with DMA_ATTR_WRITE_BARRIER would prevent the race.

DMA_ATTR_WEAK_ORDERING

----------------------

DMA_ATTR_WEAK_ORDERING specifies that reads and writes to the mapping

may be weakly ordered, that is that reads and writes may pass each other.

Since it is optional for platforms to implement DMA_ATTR_WEAK_ORDERING,

those that do not will simply ignore the attribute and exhibit default

behavior.

    3) OpenPIC Interrupt Controllers

    4) ISA Interrupt Controllers

  VIII - Specifying GPIO information for devices

  IX - Specifying GPIO information for devices

    1) gpios property

    2) gpio-controller nodes

  X - Specifying device power management information (sleep property)

  Appendix A - Sample SOC node for MPC8540

	2 =  high to low edge sensitive type enabled

	3 =  low to high edge sensitive type enabled

VIII - Specifying GPIO information for devices

==============================================

IX - Specifying GPIO information for devices

============================================

1) gpios property

-----------------

		gpio-controller;

	};

X - Specifying Device Power Management Information (sleep property)

===================================================================

Devices on SOCs often have mechanisms for placing devices into low-power

states that are decoupled from the devices' own register blocks.  Sometimes,

this information is more complicated than a cell-index property can

reasonably describe.  Thus, each device controlled in such a manner

may contain a "sleep" property which describes these connections.

The sleep property consists of one or more sleep resources, each of

which consists of a phandle to a sleep controller, followed by a

controller-specific sleep specifier of zero or more cells.

The semantics of what type of low power modes are possible are defined

by the sleep controller.  Some examples of the types of low power modes

that may be supported are:

 - Dynamic: The device may be disabled or enabled at any time.

 - System Suspend: The device may request to be disabled or remain

   awake during system suspend, but will not be disabled until then.

 - Permanent: The device is disabled permanently (until the next hard

   reset).

Some devices may share a clock domain with each other, such that they should

only be suspended when none of the devices are in use.  Where reasonable,

such nodes should be placed on a virtual bus, where the bus has the sleep

property.  If the clock domain is shared among devices that cannot be

reasonably grouped in this manner, then create a virtual sleep controller

(similar to an interrupt nexus, except that defining a standardized

sleep-map should wait until its necessity is demonstrated).

Appendix A - Sample SOC node for MPC8540

========================================

Note that the #address-cells and #size-cells for the SoC node

in this example have been explicitly listed; these are likely

not necessary as they are usually the same as the root node.

	soc8540@e0000000 {

	soc@e0000000 {

		#address-cells = <1>;

		#size-cells = <1>;

		#interrupt-cells = <2>;

		compatible = "fsl,mpc8540-ccsr", "simple-bus";

		device_type = "soc";

		ranges = <00000000 e0000000 00100000>

		reg = <e0000000 00003000>;

		ranges = <0x00000000 0xe0000000 0x00100000>

		bus-frequency = <0>;

		interrupt-parent = <&pic>;

		ethernet@24000 {

			#address-cells = <1>;

			#size-cells = <1>;

			device_type = "network";

			model = "TSEC";

			compatible = "gianfar", "simple-bus";

			reg = <0x24000 0x1000>;

			local-mac-address = [ 00 E0 0C 00 73 00 ];

			interrupts = <29 2 30 2 34 2>;

			phy-handle = <&phy0>;

			sleep = <&pmc 00000080>;

			ranges;

			mdio@24520 {

			reg = <24520 20>;

			device_type = "mdio";

			compatible = "gianfar";

				reg = <0x24520 0x20>;

				compatible = "fsl,gianfar-mdio";

			ethernet-phy@0 {

				linux,phandle = <2452000>

				interrupt-parent = <40000>;

				interrupts = <35 1>;

				phy0: ethernet-phy@0 {

					interrupts = <5 1>;

					reg = <0>;

					device_type = "ethernet-phy";

				};

			ethernet-phy@1 {

				linux,phandle = <2452001>

				interrupt-parent = <40000>;

				interrupts = <35 1>;

				phy1: ethernet-phy@1 {

					interrupts = <5 1>;

					reg = <1>;

					device_type = "ethernet-phy";

				};

			ethernet-phy@3 {

				linux,phandle = <2452002>

				interrupt-parent = <40000>;

				interrupts = <35 1>;

				phy3: ethernet-phy@3 {

					interrupts = <7 1>;

					reg = <3>;

					device_type = "ethernet-phy";

				};

			};

		ethernet@24000 {

			#size-cells = <0>;

			device_type = "network";

			model = "TSEC";

			compatible = "gianfar";

			reg = <24000 1000>;

			mac-address = [ 00 E0 0C 00 73 00 ];

			interrupts = <d 3 e 3 12 3>;

			interrupt-parent = <40000>;

			phy-handle = <2452000>;

		};

		ethernet@25000 {

			#address-cells = <1>;

			#size-cells = <0>;

			device_type = "network";

			model = "TSEC";

			compatible = "gianfar";

			reg = <25000 1000>;

			mac-address = [ 00 E0 0C 00 73 01 ];

			interrupts = <13 3 14 3 18 3>;

			interrupt-parent = <40000>;

			phy-handle = <2452001>;

			reg = <0x25000 0x1000>;

			local-mac-address = [ 00 E0 0C 00 73 01 ];

			interrupts = <13 2 14 2 18 2>;

			phy-handle = <&phy1>;

			sleep = <&pmc 00000040>;

		};

		ethernet@26000 {

			#address-cells = <1>;

			#size-cells = <0>;

			device_type = "network";

			model = "FEC";

			compatible = "gianfar";

			reg = <26000 1000>;

			mac-address = [ 00 E0 0C 00 73 02 ];

			interrupts = <19 3>;

			interrupt-parent = <40000>;

			phy-handle = <2452002>;

			reg = <0x26000 0x1000>;

			local-mac-address = [ 00 E0 0C 00 73 02 ];

			interrupts = <41 2>;

			phy-handle = <&phy3>;

			sleep = <&pmc 00000020>;

		};

		serial@4500 {

			#address-cells = <1>;

			#size-cells = <1>;

			compatible = "fsl,mpc8540-duart", "simple-bus";

			sleep = <&pmc 00000002>;

			ranges;

			serial@4500 {

				device_type = "serial";

				compatible = "ns16550";

			reg = <4500 100>;

				reg = <0x4500 0x100>;

				clock-frequency = <0>;

			interrupts = <1a 3>;

			interrupt-parent = <40000>;

				interrupts = <42 2>;

			};

		pic@40000 {

			linux,phandle = <40000>;

			serial@4600 {

				device_type = "serial";

				compatible = "ns16550";

				reg = <0x4600 0x100>;

				clock-frequency = <0>;

				interrupts = <42 2>;

			};

		};

		pic: pic@40000 {

			interrupt-controller;

			#address-cells = <0>;

			reg = <40000 40000>;

			#interrupt-cells = <2>;

			reg = <0x40000 0x40000>;

			compatible = "chrp,open-pic";

			device_type = "open-pic";

		};

		i2c@3000 {

			interrupt-parent = <40000>;

			interrupts = <1b 3>;

			reg = <3000 18>;

			device_type = "i2c";

			interrupts = <43 2>;

			reg = <0x3000 0x100>;

			compatible  = "fsl-i2c";

			dfsrr;

			sleep = <&pmc 00000004>;

		};

		pmc: power@e0070 {

			compatible = "fsl,mpc8540-pmc", "fsl,mpc8548-pmc";

			reg = <0xe0070 0x20>;

		};

	};

Every GPIO controller node must have #gpio-cells property defined,

this information will be used to translate gpio-specifiers.

On CPM1 devices, all ports are using slightly different register layouts.

Ports A, C and D are 16bit ports and Ports B and E are 32bit ports.

On CPM2 devices, all ports are 32bit ports and use a common register layout.

Required properties:

- compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b",

  "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d",

  "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank"

- #gpio-cells : Should be two. The first cell is the pin number and the

  second cell is used to specify optional paramters (currently unused).

- gpio-controller : Marks the port as GPIO controller.

Example of three SOC GPIO banks defined as gpio-controller nodes:

	CPM1_PIO_A: gpio-controller@950 {

		#gpio-cells = <2>;

		compatible = "fsl,cpm1-pario-bank-a";

		reg = <0x950 0x10>;

		gpio-controller;

	};

	CPM1_PIO_B: gpio-controller@ab8 {

		#gpio-cells = <2>;

		compatible = "fsl,cpm1-pario-bank-b";

		reg = <0xab8 0x10>;

		gpio-controller;

	};

	CPM1_PIO_E: gpio-controller@ac8 {

		#gpio-cells = <2>;

		compatible = "fsl,cpm1-pario-bank-e";

		reg = <0xac8 0x18>;

		gpio-controller;

	};

* USB (Universal Serial Bus Controller)

Freescale QUICC Engine USB Controller

Required properties:

- compatible : could be "qe_udc" or "fhci-hcd".

- mode : the could be "host" or "slave".

- reg : Offset and length of the register set for the device

- interrupts : <a b> where a is the interrupt number and b is a

  field that represents an encoding of the sense and level

  information for the interrupt.  This should be encoded based on

  the information in section 2) depending on the type of interrupt

  controller you have.

- interrupt-parent : the phandle for the interrupt controller that

  services interrupts for this device.

- compatible : should be "fsl,<chip>-qe-usb", "fsl,mpc8323-qe-usb".

- reg : the first two cells should contain usb registers location and

  length, the next two two cells should contain PRAM location and

  length.

- interrupts : should contain USB interrupt.

- interrupt-parent : interrupt source phandle.

- fsl,fullspeed-clock : specifies the full speed USB clock source:

  "none": clock source is disabled

  "brg1" through "brg16": clock source is BRG1-BRG16, respectively

  "clk1" through "clk24": clock source is CLK1-CLK24, respectively

- fsl,lowspeed-clock : specifies the low speed USB clock source:

  "none": clock source is disabled

  "brg1" through "brg16": clock source is BRG1-BRG16, respectively

  "clk1" through "clk24": clock source is CLK1-CLK24, respectively

- hub-power-budget : USB power budget for the root hub, in mA.

- gpios : should specify GPIOs in this order: USBOE, USBTP, USBTN, USBRP,

  USBRN, SPEED (optional), and POWER (optional).

Example:

Example(slave):

usb@6c0 {

		compatible = "qe_udc";

		reg = <6c0 40>;

		interrupts = <8b 0>;

		interrupt-parent = <700>;

		mode = "slave";

	compatible = "fsl,mpc8360-qe-usb", "fsl,mpc8323-qe-usb";

	reg = <0x6c0 0x40 0x8b00 0x100>;

	interrupts = <11>;

	interrupt-parent = <&qeic>;

	fsl,fullspeed-clock = "clk21";

	gpios = <&qe_pio_b  2 0 /* USBOE */

		 &qe_pio_b  3 0 /* USBTP */

		 &qe_pio_b  8 0 /* USBTN */

		 &qe_pio_b  9 0 /* USBRP */

		 &qe_pio_b 11 0 /* USBRN */

		 &qe_pio_e 20 0 /* SPEED */

		 &qe_pio_e 21 0 /* POWER */>;

};

Freescale MPC8349E-mITX-compatible Power Management Micro Controller Unit (MCU)

Required properties:

- compatible : "fsl,<mcu-chip>-<board>", "fsl,mcu-mpc8349emitx".

- reg : should specify I2C address (0x0a).

- #gpio-cells : should be 2.

- gpio-controller : should be present.

Example:

mcu@0a {

	#gpio-cells = <2>;

	compatible = "fsl,mc9s08qg8-mpc8349emitx",

		     "fsl,mcu-mpc8349emitx";

	reg = <0x0a>;

	gpio-controller;

};