Commit 06b439de authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'hinic-add-SR-IOV-support' 



Luo bin says:

====================
hinic: add SR-IOV support

patch #1 adds mailbox channel support and vf can
communicate with pf or hw through it.
patch #2 adds support for enabling vf and tx/rx
capabilities based on vf.
patch #3 adds support for vf's basic configurations.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents c90af587 1f62cfa1

drivers/net/ethernet/huawei/hinic/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -4,4 +4,4 @@ obj-$(CONFIG_HINIC) += hinic.o 
hinic-y := hinic_main.o hinic_tx.o hinic_rx.o hinic_port.o hinic_hw_dev.o \

	   hinic_hw_io.o hinic_hw_qp.o hinic_hw_cmdq.o hinic_hw_wq.o \

	   hinic_hw_mgmt.o hinic_hw_api_cmd.o hinic_hw_eqs.o hinic_hw_if.o \

	   hinic_common.o hinic_ethtool.o
 
	   hinic_common.o hinic_ethtool.o hinic_hw_mbox.o hinic_sriov.o

drivers/net/ethernet/huawei/hinic/hinic_dev.h

+3 −0
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ 
#include "hinic_hw_dev.h"

#include "hinic_tx.h"

#include "hinic_rx.h"

#include "hinic_sriov.h"



#define HINIC_DRV_NAME          "hinic"
@@ -23,6 +24,7 @@ enum hinic_flags { 
	HINIC_LINK_UP = BIT(0),

	HINIC_INTF_UP = BIT(1),

	HINIC_RSS_ENABLE = BIT(2),

	HINIC_LINK_DOWN = BIT(3),

};



struct hinic_rx_mode_work {
@@ -78,6 +80,7 @@ struct hinic_dev { 
	struct hinic_rss_type		rss_type;

	u8				*rss_hkey_user;

	s32				*rss_indir_user;

	struct hinic_sriov_info sriov_info;

};



#endif

drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.c

+8 −10
Original line number Diff line number Diff line
@@ -64,7 +64,7 @@ 
#define CMDQ_WQE_SIZE                   64

#define CMDQ_DEPTH                      SZ_4K



#define CMDQ_WQ_PAGE_SIZE               SZ_4K

#define CMDQ_WQ_PAGE_SIZE               SZ_256K



#define WQE_LCMD_SIZE                   64

#define WQE_SCMD_SIZE                   64
@@ -705,7 +705,7 @@ static void cmdq_init_queue_ctxt(struct hinic_cmdq_ctxt *cmdq_ctxt, 
	/* The data in the HW is in Big Endian Format */

	wq_first_page_paddr = be64_to_cpu(*wq->block_vaddr);



	pfn = CMDQ_PFN(wq_first_page_paddr, wq->wq_page_size);

	pfn = CMDQ_PFN(wq_first_page_paddr, SZ_4K);



	ctxt_info->curr_wqe_page_pfn =

		HINIC_CMDQ_CTXT_PAGE_INFO_SET(pfn, CURR_WQE_PAGE_PFN)   |
@@ -714,16 +714,19 @@ static void cmdq_init_queue_ctxt(struct hinic_cmdq_ctxt *cmdq_ctxt, 
		HINIC_CMDQ_CTXT_PAGE_INFO_SET(1, CEQ_EN)                |

		HINIC_CMDQ_CTXT_PAGE_INFO_SET(cmdq->wrapped, WRAPPED);



	if (wq->num_q_pages != 1) {

		/* block PFN - Read Modify Write */

		cmdq_first_block_paddr = cmdq_pages->page_paddr;



		pfn = CMDQ_PFN(cmdq_first_block_paddr, wq->wq_page_size);

	}



	ctxt_info->wq_block_pfn =

		HINIC_CMDQ_CTXT_BLOCK_INFO_SET(pfn, WQ_BLOCK_PFN) |

		HINIC_CMDQ_CTXT_BLOCK_INFO_SET(atomic_read(&wq->cons_idx), CI);



	cmdq_ctxt->func_idx = HINIC_HWIF_FUNC_IDX(cmdqs->hwif);

	cmdq_ctxt->ppf_idx = HINIC_HWIF_PPF_IDX(cmdqs->hwif);

	cmdq_ctxt->cmdq_type  = cmdq->cmdq_type;

}
@@ -795,11 +798,6 @@ static int init_cmdqs_ctxt(struct hinic_hwdev *hwdev, 
	size_t cmdq_ctxts_size;

	int err;



	if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) {

		dev_err(&pdev->dev, "Unsupported PCI function type\n");

		return -EINVAL;

	}



	cmdq_ctxts_size = HINIC_MAX_CMDQ_TYPES * sizeof(*cmdq_ctxts);

	cmdq_ctxts = devm_kzalloc(&pdev->dev, cmdq_ctxts_size, GFP_KERNEL);

	if (!cmdq_ctxts)

drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h

+1 −1
Original line number Diff line number Diff line
@@ -122,7 +122,7 @@ struct hinic_cmdq_ctxt { 


	u16     func_idx;

	u8      cmdq_type;

	u8      rsvd1[1];

	u8      ppf_idx;



	u8      rsvd2[4];

drivers/net/ethernet/huawei/hinic/hinic_hw_csr.h

+1 −1
Original line number Diff line number Diff line
@@ -10,7 +10,7 @@ 
/* HW interface registers */

#define HINIC_CSR_FUNC_ATTR0_ADDR                       0x0

#define HINIC_CSR_FUNC_ATTR1_ADDR                       0x4



#define HINIC_CSR_FUNC_ATTR2_ADDR			0x8

#define HINIC_CSR_FUNC_ATTR4_ADDR                       0x10

#define HINIC_CSR_FUNC_ATTR5_ADDR                       0x14

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