Commit 06a80a7d authored by Jose Abreu's avatar Jose Abreu Committed by David S. Miller
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net: stmmac: Fix descriptors address being in > 32 bits address space 



Commit a993db88 ("net: stmmac: Enable support for > 32 Bits
addressing in XGMAC"), introduced support for > 32 bits addressing in
XGMAC but the conversion of descriptors to dma_addr_t was left out.

As some devices assing coherent memory in regions > 32 bits we need to
set lower and upper value of descriptors address when initializing DMA
channels.

Luckly, this was working for me because I was assigning CMA to < 4GB
address space for performance reasons.

Fixes: a993db88 ("net: stmmac: Enable support for > 32 Bits addressing in XGMAC")
Signed-off-by: default avatarJose Abreu <joabreu@synopsys.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent d429b66e

drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c

+4 −4
Original line number Diff line number Diff line
@@ -289,18 +289,18 @@ static void sun8i_dwmac_dma_init(void __iomem *ioaddr, 


static void sun8i_dwmac_dma_init_rx(void __iomem *ioaddr,

				    struct stmmac_dma_cfg *dma_cfg,

				    u32 dma_rx_phy, u32 chan)

				    dma_addr_t dma_rx_phy, u32 chan)

{

	/* Write RX descriptors address */

	writel(dma_rx_phy, ioaddr + EMAC_RX_DESC_LIST);

	writel(lower_32_bits(dma_rx_phy), ioaddr + EMAC_RX_DESC_LIST);

}



static void sun8i_dwmac_dma_init_tx(void __iomem *ioaddr,

				    struct stmmac_dma_cfg *dma_cfg,

				    u32 dma_tx_phy, u32 chan)

				    dma_addr_t dma_tx_phy, u32 chan)

{

	/* Write TX descriptors address */

	writel(dma_tx_phy, ioaddr + EMAC_TX_DESC_LIST);

	writel(lower_32_bits(dma_tx_phy), ioaddr + EMAC_TX_DESC_LIST);

}



/* sun8i_dwmac_dump_regs() - Dump EMAC address space

drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c

+4 −4
Original line number Diff line number Diff line
@@ -112,18 +112,18 @@ static void dwmac1000_dma_init(void __iomem *ioaddr, 


static void dwmac1000_dma_init_rx(void __iomem *ioaddr,

				  struct stmmac_dma_cfg *dma_cfg,

				  u32 dma_rx_phy, u32 chan)

				  dma_addr_t dma_rx_phy, u32 chan)

{

	/* RX descriptor base address list must be written into DMA CSR3 */

	writel(dma_rx_phy, ioaddr + DMA_RCV_BASE_ADDR);

	writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_RCV_BASE_ADDR);

}



static void dwmac1000_dma_init_tx(void __iomem *ioaddr,

				  struct stmmac_dma_cfg *dma_cfg,

				  u32 dma_tx_phy, u32 chan)

				  dma_addr_t dma_tx_phy, u32 chan)

{

	/* TX descriptor base address list must be written into DMA CSR4 */

	writel(dma_tx_phy, ioaddr + DMA_TX_BASE_ADDR);

	writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_TX_BASE_ADDR);

}



static u32 dwmac1000_configure_fc(u32 csr6, int rxfifosz)

drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c

+4 −4
Original line number Diff line number Diff line
@@ -31,18 +31,18 @@ static void dwmac100_dma_init(void __iomem *ioaddr, 


static void dwmac100_dma_init_rx(void __iomem *ioaddr,

				 struct stmmac_dma_cfg *dma_cfg,

				 u32 dma_rx_phy, u32 chan)

				 dma_addr_t dma_rx_phy, u32 chan)

{

	/* RX descriptor base addr lists must be written into DMA CSR3 */

	writel(dma_rx_phy, ioaddr + DMA_RCV_BASE_ADDR);

	writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_RCV_BASE_ADDR);

}



static void dwmac100_dma_init_tx(void __iomem *ioaddr,

				 struct stmmac_dma_cfg *dma_cfg,

				 u32 dma_tx_phy, u32 chan)

				 dma_addr_t dma_tx_phy, u32 chan)

{

	/* TX descriptor base addr lists must be written into DMA CSR4 */

	writel(dma_tx_phy, ioaddr + DMA_TX_BASE_ADDR);

	writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_TX_BASE_ADDR);

}



/* Store and Forward capability is not used at all.

drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c

+4 −4
Original line number Diff line number Diff line
@@ -70,7 +70,7 @@ static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) 


static void dwmac4_dma_init_rx_chan(void __iomem *ioaddr,

				    struct stmmac_dma_cfg *dma_cfg,

				    u32 dma_rx_phy, u32 chan)

				    dma_addr_t dma_rx_phy, u32 chan)

{

	u32 value;

	u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
@@ -79,12 +79,12 @@ static void dwmac4_dma_init_rx_chan(void __iomem *ioaddr, 
	value = value | (rxpbl << DMA_BUS_MODE_RPBL_SHIFT);

	writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan));



	writel(dma_rx_phy, ioaddr + DMA_CHAN_RX_BASE_ADDR(chan));

	writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_CHAN_RX_BASE_ADDR(chan));

}



static void dwmac4_dma_init_tx_chan(void __iomem *ioaddr,

				    struct stmmac_dma_cfg *dma_cfg,

				    u32 dma_tx_phy, u32 chan)

				    dma_addr_t dma_tx_phy, u32 chan)

{

	u32 value;

	u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
@@ -97,7 +97,7 @@ static void dwmac4_dma_init_tx_chan(void __iomem *ioaddr, 


	writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan));



	writel(dma_tx_phy, ioaddr + DMA_CHAN_TX_BASE_ADDR(chan));

	writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_CHAN_TX_BASE_ADDR(chan));

}



static void dwmac4_dma_init_channel(void __iomem *ioaddr,

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

+2 −0
Original line number Diff line number Diff line
@@ -199,7 +199,9 @@ 
#define XGMAC_RxPBL			GENMASK(21, 16)

#define XGMAC_RxPBL_SHIFT		16

#define XGMAC_RXST			BIT(0)

#define XGMAC_DMA_CH_TxDESC_HADDR(x)	(0x00003110 + (0x80 * (x)))

#define XGMAC_DMA_CH_TxDESC_LADDR(x)	(0x00003114 + (0x80 * (x)))

#define XGMAC_DMA_CH_RxDESC_HADDR(x)	(0x00003118 + (0x80 * (x)))

#define XGMAC_DMA_CH_RxDESC_LADDR(x)	(0x0000311c + (0x80 * (x)))

#define XGMAC_DMA_CH_TxDESC_TAIL_LPTR(x)	(0x00003124 + (0x80 * (x)))

#define XGMAC_DMA_CH_RxDESC_TAIL_LPTR(x)	(0x0000312c + (0x80 * (x)))

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