Commit 06930b94 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu 

Pull m68knommu tree from Greg Ungerer:
 "More merge and clean up of MMU and non-MMU common files, namely
  signal.c and dma.c.  There is also a simplification of the ColdFire
  GPIO setup tables.  Using a couple of simple macros we make the init
  tables really small and easy to read, and save a couple of thousand
  lines of code.  Also a move of all the ColdFire subarch support files
  into the existing coldfire directory.  The sub-directories just ended
  up duplicating Makefiles and now only contain really simple pieces of
  code.  This saves quite a few lines of code too.

  As always a couple of bugs fixes thrown in too.  Oh and a new
  defconfig for the ColdFire platforms that support having the MMU
  enabled."

* 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: (39 commits)
  m68k: add a defconfig for the M5475EVB ColdFire with MMU board
  m68knommu: unaligned.h fix for M68000 core
  m68k: merge the MMU and non-MMU versions of the arch dma code
  m68knommu: reorganize the no-MMU cache flushing to match m68k
  m68knommu: move the 54xx platform code into the common ColdFire code directory
  m68knommu: move the 532x platform code into the common ColdFire code directory
  m68knommu: move the 5407 platform code into the common ColdFire code directory
  m68knommu: move the 5307 platform code into the common ColdFire code directory
  m68knommu: move the 528x platform code into the common ColdFire code directory
  m68knommu: move the 527x platform code into the common ColdFire code directory
  m68knommu: move the 5272 platform code into the common ColdFire code directory
  m68knommu: move the 5249 platform code into the common ColdFire code directory
  m68knommu: move the 523x platform code into the common ColdFire code directory
  m68knommu: move the 520x platform code into the common ColdFire code directory
  m68knommu: move the 5206 platform code into the common ColdFire code directory
  m68knommu: simplify the ColdFire 5407 GPIO struct setup
  m68knommu: simplify the ColdFire 532x GPIO struct setup
  m68knommu: simplify the ColdFire 5307 GPIO struct setup
  m68knommu: simplify the ColdFire 528x GPIO struct setup
  m68knommu: simplify the ColdFire 527x GPIO struct setup
  ...
parents 2e321806 7094ac08

arch/m68k/Makefile

+0 −12
Original line number Diff line number Diff line
@@ -116,18 +116,6 @@ core-$(CONFIG_M68000) += arch/m68k/platform/68328/ 
core-$(CONFIG_M68EZ328)		+= arch/m68k/platform/68EZ328/

core-$(CONFIG_M68VZ328)		+= arch/m68k/platform/68VZ328/

core-$(CONFIG_COLDFIRE)		+= arch/m68k/platform/coldfire/

core-$(CONFIG_M5206)		+= arch/m68k/platform/5206/

core-$(CONFIG_M5206e)		+= arch/m68k/platform/5206/

core-$(CONFIG_M520x)		+= arch/m68k/platform/520x/

core-$(CONFIG_M523x)		+= arch/m68k/platform/523x/

core-$(CONFIG_M5249)		+= arch/m68k/platform/5249/

core-$(CONFIG_M527x)		+= arch/m68k/platform/527x/

core-$(CONFIG_M5272)		+= arch/m68k/platform/5272/

core-$(CONFIG_M528x)		+= arch/m68k/platform/528x/

core-$(CONFIG_M5307)		+= arch/m68k/platform/5307/

core-$(CONFIG_M532x)		+= arch/m68k/platform/532x/

core-$(CONFIG_M5407)		+= arch/m68k/platform/5407/

core-$(CONFIG_M54xx)		+= arch/m68k/platform/54xx/





all:	zImage

arch/m68k/configs/m5475evb_defconfig

0 → 100644
+62 −0
Original line number Diff line number Diff line 
CONFIG_EXPERIMENTAL=y

# CONFIG_SWAP is not set

CONFIG_LOG_BUF_SHIFT=14

CONFIG_SYSFS_DEPRECATED=y

CONFIG_SYSFS_DEPRECATED_V2=y

CONFIG_SYSCTL_SYSCALL=y

# CONFIG_KALLSYMS is not set

# CONFIG_HOTPLUG is not set

# CONFIG_FUTEX is not set

# CONFIG_EPOLL is not set

# CONFIG_SIGNALFD is not set

# CONFIG_TIMERFD is not set

# CONFIG_EVENTFD is not set

# CONFIG_SHMEM is not set

# CONFIG_AIO is not set

CONFIG_EMBEDDED=y

CONFIG_MODULES=y

# CONFIG_LBDAF is not set

# CONFIG_BLK_DEV_BSG is not set

# CONFIG_IOSCHED_DEADLINE is not set

# CONFIG_IOSCHED_CFQ is not set

CONFIG_COLDFIRE=y

CONFIG_M547x=y

CONFIG_CLOCK_SET=y

CONFIG_CLOCK_FREQ=266000000

# CONFIG_4KSTACKS is not set

CONFIG_RAMBASE=0x0

CONFIG_RAMSIZE=0x2000000

CONFIG_VECTORBASE=0x0

CONFIG_MBAR=0xff000000

CONFIG_KERNELBASE=0x20000

# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set

# CONFIG_FW_LOADER is not set

CONFIG_MTD=y

CONFIG_MTD_CHAR=y

CONFIG_MTD_BLOCK=y

CONFIG_MTD_CFI=y

CONFIG_MTD_JEDECPROBE=y

CONFIG_MTD_CFI_AMDSTD=y

CONFIG_MTD_RAM=y

CONFIG_MTD_PHYSMAP=y

CONFIG_MTD_UCLINUX=y

CONFIG_BLK_DEV_RAM=y

# CONFIG_INPUT is not set

# CONFIG_VT is not set

# CONFIG_UNIX98_PTYS is not set

CONFIG_SERIAL_MCF=y

CONFIG_SERIAL_MCF_CONSOLE=y

# CONFIG_HW_RANDOM is not set

# CONFIG_HWMON is not set

# CONFIG_USB_SUPPORT is not set

# CONFIG_IOMMU_SUPPORT is not set

CONFIG_EXT2_FS=y

# CONFIG_FILE_LOCKING is not set

# CONFIG_DNOTIFY is not set

# CONFIG_INOTIFY_USER is not set

# CONFIG_PROC_PAGE_MONITOR is not set

CONFIG_ROMFS_FS=y

CONFIG_ROMFS_BACKED_BY_MTD=y

# CONFIG_SCHED_DEBUG is not set

CONFIG_BOOTPARAM=y

CONFIG_BOOTPARAM_STRING="root=/dev/mtdblock0"

arch/m68k/include/asm/cacheflush_no.h

+28 −4
Original line number Diff line number Diff line
@@ -30,11 +30,8 @@ 


void mcf_cache_push(void);



static inline void __flush_cache_all(void)

static inline void __clear_cache_all(void)

{

#ifdef CACHE_PUSH

	mcf_cache_push();

#endif

#ifdef CACHE_INVALIDATE

	__asm__ __volatile__ (

		"movel	%0, %%d0\n\t"
@@ -44,6 +41,14 @@ static inline void __flush_cache_all(void) 
#endif

}



static inline void __flush_cache_all(void)

{

#ifdef CACHE_PUSH

	mcf_cache_push();

#endif

	__clear_cache_all();

}



/*

 * Some ColdFire parts implement separate instruction and data caches,

 * on those we should just flush the appropriate cache. If we don't need
@@ -76,4 +81,23 @@ static inline void __flush_dcache_all(void) 
	__asm__ __volatile__ ( "nop" );

#endif

}



/*

 * Push cache entries at supplied address. We want to write back any dirty

 * data and the invalidate the cache lines associated with this address.

 */

static inline void cache_push(unsigned long paddr, int len)

{

	__flush_cache_all();

}



/*

 * Clear cache entries at supplied address (that is don't write back any

 * dirty data).

 */

static inline void cache_clear(unsigned long paddr, int len)

{

	__clear_cache_all();

}



#endif /* _M68KNOMMU_CACHEFLUSH_H */

arch/m68k/include/asm/flat.h

+6 −1
Original line number Diff line number Diff line
@@ -11,6 +11,11 @@ 
#define	flat_get_addr_from_rp(rp, relval, flags, p)	get_unaligned(rp)

#define	flat_put_addr_at_rp(rp, val, relval)	put_unaligned(val,rp)

#define	flat_get_relocate_addr(rel)		(rel)

#define	flat_set_persistent(relval, p)		0



static inline int flat_set_persistent(unsigned long relval,

				      unsigned long *persistent)

{

	return 0;

}



#endif /* __M68KNOMMU_FLAT_H__ */

arch/m68k/include/asm/m528xsim.h

+80 −99
Original line number Diff line number Diff line
@@ -97,100 +97,81 @@ 
/*

 * 	GPIO registers

 */

#define MCFGPIO_PORTA		(MCF_IPSBAR + 0x00100000)

#define MCFGPIO_PORTB		(MCF_IPSBAR + 0x00100001)

#define MCFGPIO_PORTC		(MCF_IPSBAR + 0x00100002)

#define MCFGPIO_PORTD		(MCF_IPSBAR + 0x00100003)

#define MCFGPIO_PORTE		(MCF_IPSBAR + 0x00100004)

#define MCFGPIO_PORTF		(MCF_IPSBAR + 0x00100005)

#define MCFGPIO_PORTG		(MCF_IPSBAR + 0x00100006)

#define MCFGPIO_PORTH		(MCF_IPSBAR + 0x00100007)

#define MCFGPIO_PORTJ		(MCF_IPSBAR + 0x00100008)

#define MCFGPIO_PORTDD		(MCF_IPSBAR + 0x00100009)

#define MCFGPIO_PORTEH		(MCF_IPSBAR + 0x0010000A)

#define MCFGPIO_PORTEL		(MCF_IPSBAR + 0x0010000B)

#define MCFGPIO_PORTAS		(MCF_IPSBAR + 0x0010000C)

#define MCFGPIO_PORTQS		(MCF_IPSBAR + 0x0010000D)

#define MCFGPIO_PORTSD		(MCF_IPSBAR + 0x0010000E)

#define MCFGPIO_PORTTC		(MCF_IPSBAR + 0x0010000F)

#define MCFGPIO_PORTTD		(MCF_IPSBAR + 0x00100010)

#define MCFGPIO_PORTUA		(MCF_IPSBAR + 0x00100011)



#define MCFGPIO_DDRA		(MCF_IPSBAR + 0x00100014)

#define MCFGPIO_DDRB		(MCF_IPSBAR + 0x00100015)

#define MCFGPIO_DDRC		(MCF_IPSBAR + 0x00100016)

#define MCFGPIO_DDRD		(MCF_IPSBAR + 0x00100017)

#define MCFGPIO_DDRE		(MCF_IPSBAR + 0x00100018)

#define MCFGPIO_DDRF		(MCF_IPSBAR + 0x00100019)

#define MCFGPIO_DDRG		(MCF_IPSBAR + 0x0010001A)

#define MCFGPIO_DDRH		(MCF_IPSBAR + 0x0010001B)

#define MCFGPIO_DDRJ		(MCF_IPSBAR + 0x0010001C)

#define MCFGPIO_DDRDD		(MCF_IPSBAR + 0x0010001D)

#define MCFGPIO_DDREH		(MCF_IPSBAR + 0x0010001E)

#define MCFGPIO_DDREL		(MCF_IPSBAR + 0x0010001F)

#define MCFGPIO_DDRAS		(MCF_IPSBAR + 0x00100020)

#define MCFGPIO_DDRQS		(MCF_IPSBAR + 0x00100021)

#define MCFGPIO_DDRSD		(MCF_IPSBAR + 0x00100022)

#define MCFGPIO_DDRTC		(MCF_IPSBAR + 0x00100023)

#define MCFGPIO_DDRTD		(MCF_IPSBAR + 0x00100024)

#define MCFGPIO_DDRUA		(MCF_IPSBAR + 0x00100025)



#define MCFGPIO_PORTAP		(MCF_IPSBAR + 0x00100028)

#define MCFGPIO_PORTBP		(MCF_IPSBAR + 0x00100029)

#define MCFGPIO_PORTCP		(MCF_IPSBAR + 0x0010002A)

#define MCFGPIO_PORTDP		(MCF_IPSBAR + 0x0010002B)

#define MCFGPIO_PORTEP		(MCF_IPSBAR + 0x0010002C)

#define MCFGPIO_PORTFP		(MCF_IPSBAR + 0x0010002D)

#define MCFGPIO_PORTGP		(MCF_IPSBAR + 0x0010002E)

#define MCFGPIO_PORTHP		(MCF_IPSBAR + 0x0010002F)

#define MCFGPIO_PORTJP		(MCF_IPSBAR + 0x00100030)

#define MCFGPIO_PORTDDP		(MCF_IPSBAR + 0x00100031)

#define MCFGPIO_PORTEHP		(MCF_IPSBAR + 0x00100032)

#define MCFGPIO_PORTELP		(MCF_IPSBAR + 0x00100033)

#define MCFGPIO_PORTASP		(MCF_IPSBAR + 0x00100034)

#define MCFGPIO_PORTQSP		(MCF_IPSBAR + 0x00100035)

#define MCFGPIO_PORTSDP		(MCF_IPSBAR + 0x00100036)

#define MCFGPIO_PORTTCP		(MCF_IPSBAR + 0x00100037)

#define MCFGPIO_PORTTDP		(MCF_IPSBAR + 0x00100038)

#define MCFGPIO_PORTUAP		(MCF_IPSBAR + 0x00100039)



#define MCFGPIO_SETA		(MCF_IPSBAR + 0x00100028)

#define MCFGPIO_SETB		(MCF_IPSBAR + 0x00100029)

#define MCFGPIO_SETC		(MCF_IPSBAR + 0x0010002A)

#define MCFGPIO_SETD		(MCF_IPSBAR + 0x0010002B)

#define MCFGPIO_SETE		(MCF_IPSBAR + 0x0010002C)

#define MCFGPIO_SETF		(MCF_IPSBAR + 0x0010002D)

#define MCFGPIO_SETG		(MCF_IPSBAR + 0x0010002E)

#define MCFGPIO_SETH		(MCF_IPSBAR + 0x0010002F)

#define MCFGPIO_SETJ		(MCF_IPSBAR + 0x00100030)

#define MCFGPIO_SETDD		(MCF_IPSBAR + 0x00100031)

#define MCFGPIO_SETEH		(MCF_IPSBAR + 0x00100032)

#define MCFGPIO_SETEL		(MCF_IPSBAR + 0x00100033)

#define MCFGPIO_SETAS		(MCF_IPSBAR + 0x00100034)

#define MCFGPIO_SETQS		(MCF_IPSBAR + 0x00100035)

#define MCFGPIO_SETSD		(MCF_IPSBAR + 0x00100036)

#define MCFGPIO_SETTC		(MCF_IPSBAR + 0x00100037)

#define MCFGPIO_SETTD		(MCF_IPSBAR + 0x00100038)

#define MCFGPIO_SETUA		(MCF_IPSBAR + 0x00100039)



#define MCFGPIO_CLRA		(MCF_IPSBAR + 0x0010003C)

#define MCFGPIO_CLRB		(MCF_IPSBAR + 0x0010003D)

#define MCFGPIO_CLRC		(MCF_IPSBAR + 0x0010003E)

#define MCFGPIO_CLRD		(MCF_IPSBAR + 0x0010003F)

#define MCFGPIO_CLRE		(MCF_IPSBAR + 0x00100040)

#define MCFGPIO_CLRF		(MCF_IPSBAR + 0x00100041)

#define MCFGPIO_CLRG		(MCF_IPSBAR + 0x00100042)

#define MCFGPIO_CLRH		(MCF_IPSBAR + 0x00100043)

#define MCFGPIO_CLRJ		(MCF_IPSBAR + 0x00100044)

#define MCFGPIO_CLRDD		(MCF_IPSBAR + 0x00100045)

#define MCFGPIO_CLREH		(MCF_IPSBAR + 0x00100046)

#define MCFGPIO_CLREL		(MCF_IPSBAR + 0x00100047)

#define MCFGPIO_CLRAS		(MCF_IPSBAR + 0x00100048)

#define MCFGPIO_CLRQS		(MCF_IPSBAR + 0x00100049)

#define MCFGPIO_CLRSD		(MCF_IPSBAR + 0x0010004A)

#define MCFGPIO_CLRTC		(MCF_IPSBAR + 0x0010004B)

#define MCFGPIO_CLRTD		(MCF_IPSBAR + 0x0010004C)

#define MCFGPIO_CLRUA		(MCF_IPSBAR + 0x0010004D)

#define MCFGPIO_PODR_A		(MCF_IPSBAR + 0x00100000)

#define MCFGPIO_PODR_B		(MCF_IPSBAR + 0x00100001)

#define MCFGPIO_PODR_C		(MCF_IPSBAR + 0x00100002)

#define MCFGPIO_PODR_D		(MCF_IPSBAR + 0x00100003)

#define MCFGPIO_PODR_E		(MCF_IPSBAR + 0x00100004)

#define MCFGPIO_PODR_F		(MCF_IPSBAR + 0x00100005)

#define MCFGPIO_PODR_G		(MCF_IPSBAR + 0x00100006)

#define MCFGPIO_PODR_H		(MCF_IPSBAR + 0x00100007)

#define MCFGPIO_PODR_J		(MCF_IPSBAR + 0x00100008)

#define MCFGPIO_PODR_DD		(MCF_IPSBAR + 0x00100009)

#define MCFGPIO_PODR_EH		(MCF_IPSBAR + 0x0010000A)

#define MCFGPIO_PODR_EL		(MCF_IPSBAR + 0x0010000B)

#define MCFGPIO_PODR_AS		(MCF_IPSBAR + 0x0010000C)

#define MCFGPIO_PODR_QS		(MCF_IPSBAR + 0x0010000D)

#define MCFGPIO_PODR_SD		(MCF_IPSBAR + 0x0010000E)

#define MCFGPIO_PODR_TC		(MCF_IPSBAR + 0x0010000F)

#define MCFGPIO_PODR_TD		(MCF_IPSBAR + 0x00100010)

#define MCFGPIO_PODR_UA		(MCF_IPSBAR + 0x00100011)



#define MCFGPIO_PDDR_A		(MCF_IPSBAR + 0x00100014)

#define MCFGPIO_PDDR_B		(MCF_IPSBAR + 0x00100015)

#define MCFGPIO_PDDR_C		(MCF_IPSBAR + 0x00100016)

#define MCFGPIO_PDDR_D		(MCF_IPSBAR + 0x00100017)

#define MCFGPIO_PDDR_E		(MCF_IPSBAR + 0x00100018)

#define MCFGPIO_PDDR_F		(MCF_IPSBAR + 0x00100019)

#define MCFGPIO_PDDR_G		(MCF_IPSBAR + 0x0010001A)

#define MCFGPIO_PDDR_H		(MCF_IPSBAR + 0x0010001B)

#define MCFGPIO_PDDR_J		(MCF_IPSBAR + 0x0010001C)

#define MCFGPIO_PDDR_DD		(MCF_IPSBAR + 0x0010001D)

#define MCFGPIO_PDDR_EH		(MCF_IPSBAR + 0x0010001E)

#define MCFGPIO_PDDR_EL		(MCF_IPSBAR + 0x0010001F)

#define MCFGPIO_PDDR_AS		(MCF_IPSBAR + 0x00100020)

#define MCFGPIO_PDDR_QS		(MCF_IPSBAR + 0x00100021)

#define MCFGPIO_PDDR_SD		(MCF_IPSBAR + 0x00100022)

#define MCFGPIO_PDDR_TC		(MCF_IPSBAR + 0x00100023)

#define MCFGPIO_PDDR_TD		(MCF_IPSBAR + 0x00100024)

#define MCFGPIO_PDDR_UA		(MCF_IPSBAR + 0x00100025)



#define MCFGPIO_PPDSDR_A	(MCF_IPSBAR + 0x00100028)

#define MCFGPIO_PPDSDR_B	(MCF_IPSBAR + 0x00100029)

#define MCFGPIO_PPDSDR_C	(MCF_IPSBAR + 0x0010002A)

#define MCFGPIO_PPDSDR_D	(MCF_IPSBAR + 0x0010002B)

#define MCFGPIO_PPDSDR_E	(MCF_IPSBAR + 0x0010002C)

#define MCFGPIO_PPDSDR_F	(MCF_IPSBAR + 0x0010002D)

#define MCFGPIO_PPDSDR_G	(MCF_IPSBAR + 0x0010002E)

#define MCFGPIO_PPDSDR_H	(MCF_IPSBAR + 0x0010002F)

#define MCFGPIO_PPDSDR_J	(MCF_IPSBAR + 0x00100030)

#define MCFGPIO_PPDSDR_DD	(MCF_IPSBAR + 0x00100031)

#define MCFGPIO_PPDSDR_EH	(MCF_IPSBAR + 0x00100032)

#define MCFGPIO_PPDSDR_EL	(MCF_IPSBAR + 0x00100033)

#define MCFGPIO_PPDSDR_AS	(MCF_IPSBAR + 0x00100034)

#define MCFGPIO_PPDSDR_QS	(MCF_IPSBAR + 0x00100035)

#define MCFGPIO_PPDSDR_SD	(MCF_IPSBAR + 0x00100036)

#define MCFGPIO_PPDSDR_TC	(MCF_IPSBAR + 0x00100037)

#define MCFGPIO_PPDSDR_TD	(MCF_IPSBAR + 0x00100038)

#define MCFGPIO_PPDSDR_UA	(MCF_IPSBAR + 0x00100039)



#define MCFGPIO_PCLRR_A		(MCF_IPSBAR + 0x0010003C)

#define MCFGPIO_PCLRR_B		(MCF_IPSBAR + 0x0010003D)

#define MCFGPIO_PCLRR_C		(MCF_IPSBAR + 0x0010003E)

#define MCFGPIO_PCLRR_D		(MCF_IPSBAR + 0x0010003F)

#define MCFGPIO_PCLRR_E		(MCF_IPSBAR + 0x00100040)

#define MCFGPIO_PCLRR_F		(MCF_IPSBAR + 0x00100041)

#define MCFGPIO_PCLRR_G		(MCF_IPSBAR + 0x00100042)

#define MCFGPIO_PCLRR_H		(MCF_IPSBAR + 0x00100043)

#define MCFGPIO_PCLRR_J		(MCF_IPSBAR + 0x00100044)

#define MCFGPIO_PCLRR_DD	(MCF_IPSBAR + 0x00100045)

#define MCFGPIO_PCLRR_EH	(MCF_IPSBAR + 0x00100046)

#define MCFGPIO_PCLRR_EL	(MCF_IPSBAR + 0x00100047)

#define MCFGPIO_PCLRR_AS	(MCF_IPSBAR + 0x00100048)

#define MCFGPIO_PCLRR_QS	(MCF_IPSBAR + 0x00100049)

#define MCFGPIO_PCLRR_SD	(MCF_IPSBAR + 0x0010004A)

#define MCFGPIO_PCLRR_TC	(MCF_IPSBAR + 0x0010004B)

#define MCFGPIO_PCLRR_TD	(MCF_IPSBAR + 0x0010004C)

#define MCFGPIO_PCLRR_UA	(MCF_IPSBAR + 0x0010004D)



#define MCFGPIO_PBCDPAR		(MCF_IPSBAR + 0x00100050)

#define MCFGPIO_PFPAR		(MCF_IPSBAR + 0x00100051)
@@ -242,11 +223,11 @@ 
 * definitions for generic gpio support

 *

 */

#define MCFGPIO_PODR		MCFGPIO_PORTA	/* port output data */

#define MCFGPIO_PDDR		MCFGPIO_DDRA	/* port data direction */

#define MCFGPIO_PPDR		MCFGPIO_PORTAP	/* port pin data */

#define MCFGPIO_SETR		MCFGPIO_SETA	/* set output */

#define MCFGPIO_CLRR		MCFGPIO_CLRA	/* clr output */

#define MCFGPIO_PODR		MCFGPIO_PODR_A	/* port output data */

#define MCFGPIO_PDDR		MCFGPIO_PDDR_A	/* port data direction */

#define MCFGPIO_PPDR		MCFGPIO_PPDSDR_A/* port pin data */

#define MCFGPIO_SETR		MCFGPIO_PPDSDR_A/* set output */

#define MCFGPIO_CLRR		MCFGPIO_PCLRR_A	/* clr output */



#define MCFGPIO_IRQ_MAX		8

#define MCFGPIO_IRQ_VECBASE	MCFINT_VECBASE

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