Commit 0688a9a9 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'net-ethernet-dwmac-add-ethernet-glue-logic-for-NXP-imx8-chip' 



Fugang Duan says:

====================
net: ethernet: dwmac: add ethernet glue logic for NXP imx8 chip

NXP imx8 family like imx8mp/imx8dxl chips support Synopsys
MAC 5.10a IP, the patch set is to add ethernet DWMAC glue
layer including clocks, dwmac address width, phy interface
mode selection and rgmii txclk rate adjustment in runtime.

v1 -> v2:
- suggested by Andrew: add the "snps,dwmac-5.10a" compatible
  string into NXP binding documentation.
- suggested by David: adjust code sequences in order to have
  reverse christmas tree local variable ordering.

Thanks Andrew and David for the review.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 8298a419 29884aa6

Documentation/devicetree/bindings/net/imx-dwmac.txt

0 → 100644
+56 −0
Original line number Diff line number Diff line 
IMX8 glue layer controller, NXP imx8 families support Synopsys MAC 5.10a IP.



This file documents platform glue layer for IMX.

Please see stmmac.txt for the other unchanged properties.



The device node has following properties.



Required properties:

- compatible:  Should be "nxp,imx8mp-dwmac-eqos" to select glue layer

	       and "snps,dwmac-5.10a" to select IP version.

- clocks: Must contain a phandle for each entry in clock-names.

- clock-names: Should be "stmmaceth" for the host clock.

	       Should be "pclk" for the MAC apb clock.

	       Should be "ptp_ref" for the MAC timer clock.

	       Should be "tx" for the MAC RGMII TX clock:

	       Should be "mem" for EQOS MEM clock.

		- "mem" clock is required for imx8dxl platform.

		- "mem" clock is not required for imx8mp platform.

- interrupt-names: Should contain a list of interrupt names corresponding to

		   the interrupts in the interrupts property, if available.

		   Should be "macirq" for the main MAC IRQ

		   Should be "eth_wake_irq" for the IT which wake up system

- intf_mode: Should be phandle/offset pair. The phandle to the syscon node which

	     encompases the GPR register, and the offset of the GPR register.

		- required for imx8mp platform.

		- is optional for imx8dxl platform.



Optional properties:

- intf_mode: is optional for imx8dxl platform.

- snps,rmii_refclk_ext: to select RMII reference clock from external.



Example:

	eqos: ethernet@30bf0000 {

		compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";

		reg = <0x30bf0000 0x10000>;

		interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "eth_wake_irq", "macirq";

		clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>,

			 <&clk IMX8MP_CLK_QOS_ENET_ROOT>,

			 <&clk IMX8MP_CLK_ENET_QOS_TIMER>,

			 <&clk IMX8MP_CLK_ENET_QOS>;

		clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";

		assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,

				  <&clk IMX8MP_CLK_ENET_QOS_TIMER>,

				  <&clk IMX8MP_CLK_ENET_QOS>;

		assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,

					 <&clk IMX8MP_SYS_PLL2_100M>,

					 <&clk IMX8MP_SYS_PLL2_125M>;

		assigned-clock-rates = <0>, <100000000>, <125000000>;

		nvmem-cells = <&eth_mac0>;

		nvmem-cell-names = "mac-address";

		nvmem_macaddr_swap;

		intf_mode = <&gpr 0x4>;

		status = "disabled";

	};

drivers/net/ethernet/stmicro/stmmac/Kconfig

+13 −0
Original line number Diff line number Diff line
@@ -196,6 +196,19 @@ config DWMAC_SUN8I 
	  This selects Allwinner SoC glue layer support for the

	  stmmac device driver. This driver is used for H3/A83T/A64

	  EMAC ethernet controller.



config DWMAC_IMX8

	tristate "NXP IMX8 DWMAC support"

	default ARCH_MXC

	depends on OF && (ARCH_MXC || COMPILE_TEST)

	select MFD_SYSCON

	---help---

	  Support for ethernet controller on NXP i.MX8 SOCs.



	  This selects NXP SoC glue layer support for the stmmac

	  device driver. This driver is used for i.MX8 series like

	  iMX8MP/iMX8DXL GMAC ethernet controller.



endif



config DWMAC_INTEL

drivers/net/ethernet/stmicro/stmmac/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ obj-$(CONFIG_DWMAC_SUNXI) += dwmac-sunxi.o 
obj-$(CONFIG_DWMAC_SUN8I)	+= dwmac-sun8i.o

obj-$(CONFIG_DWMAC_DWC_QOS_ETH)	+= dwmac-dwc-qos-eth.o

obj-$(CONFIG_DWMAC_GENERIC)	+= dwmac-generic.o

obj-$(CONFIG_DWMAC_IMX8)	+= dwmac-imx.o

stmmac-platform-objs:= stmmac_platform.o

dwmac-altr-socfpga-objs := altr_tse_pcs.o dwmac-socfpga.o

drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c

0 → 100644
+315 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * dwmac-imx.c - DWMAC Specific Glue layer for NXP imx8

 *

 * Copyright 2020 NXP

 *

 */



#include <linux/clk.h>

#include <linux/gpio/consumer.h>

#include <linux/kernel.h>

#include <linux/mfd/syscon.h>

#include <linux/module.h>

#include <linux/of.h>

#include <linux/of_device.h>

#include <linux/of_net.h>

#include <linux/phy.h>

#include <linux/platform_device.h>

#include <linux/pm_wakeirq.h>

#include <linux/regmap.h>

#include <linux/slab.h>

#include <linux/stmmac.h>



#include "stmmac_platform.h"



#define GPR_ENET_QOS_INTF_MODE_MASK	GENMASK(21, 16)

#define GPR_ENET_QOS_INTF_SEL_MII	(0x0 << 16)

#define GPR_ENET_QOS_INTF_SEL_RMII	(0x4 << 16)

#define GPR_ENET_QOS_INTF_SEL_RGMII	(0x1 << 16)

#define GPR_ENET_QOS_CLK_GEN_EN		(0x1 << 19)

#define GPR_ENET_QOS_CLK_TX_CLK_SEL	(0x1 << 20)

#define GPR_ENET_QOS_RGMII_EN		(0x1 << 21)



struct imx_dwmac_ops {

	u32 addr_width;

	bool mac_rgmii_txclk_auto_adj;



	int (*set_intf_mode)(struct plat_stmmacenet_data *plat_dat);

};



struct imx_priv_data {

	struct device *dev;

	struct clk *clk_tx;

	struct clk *clk_mem;

	struct regmap *intf_regmap;

	u32 intf_reg_off;

	bool rmii_refclk_ext;



	const struct imx_dwmac_ops *ops;

	struct plat_stmmacenet_data *plat_dat;

};



static int imx8mp_set_intf_mode(struct plat_stmmacenet_data *plat_dat)

{

	struct imx_priv_data *dwmac = plat_dat->bsp_priv;

	int val;



	switch (plat_dat->interface) {

	case PHY_INTERFACE_MODE_MII:

		val = GPR_ENET_QOS_INTF_SEL_MII;

		break;

	case PHY_INTERFACE_MODE_RMII:

		val = GPR_ENET_QOS_INTF_SEL_RMII;

		val |= (dwmac->rmii_refclk_ext ? 0 : GPR_ENET_QOS_CLK_TX_CLK_SEL);

		break;

	case PHY_INTERFACE_MODE_RGMII:

	case PHY_INTERFACE_MODE_RGMII_ID:

	case PHY_INTERFACE_MODE_RGMII_RXID:

	case PHY_INTERFACE_MODE_RGMII_TXID:

		val = GPR_ENET_QOS_INTF_SEL_RGMII |

		      GPR_ENET_QOS_RGMII_EN;

		break;

	default:

		pr_debug("imx dwmac doesn't support %d interface\n",

			 plat_dat->interface);

		return -EINVAL;

	}



	val |= GPR_ENET_QOS_CLK_GEN_EN;

	return regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off,

				  GPR_ENET_QOS_INTF_MODE_MASK, val);

};



static int

imx8dxl_set_intf_mode(struct plat_stmmacenet_data *plat_dat)

{

	int ret = 0;



	/* TBD: depends on imx8dxl scu interfaces to be upstreamed */

	return ret;

}



static int imx_dwmac_init(struct platform_device *pdev, void *priv)

{

	struct plat_stmmacenet_data *plat_dat;

	struct imx_priv_data *dwmac = priv;

	int ret;



	plat_dat = dwmac->plat_dat;



	ret = clk_prepare_enable(dwmac->clk_mem);

	if (ret) {

		dev_err(&pdev->dev, "mem clock enable failed\n");

		return ret;

	}



	ret = clk_prepare_enable(dwmac->clk_tx);

	if (ret) {

		dev_err(&pdev->dev, "tx clock enable failed\n");

		goto clk_tx_en_failed;

	}



	if (dwmac->ops->set_intf_mode) {

		ret = dwmac->ops->set_intf_mode(plat_dat);

		if (ret)

			goto intf_mode_failed;

	}



	return 0;



intf_mode_failed:

	clk_disable_unprepare(dwmac->clk_tx);

clk_tx_en_failed:

	clk_disable_unprepare(dwmac->clk_mem);

	return ret;

}



static void imx_dwmac_exit(struct platform_device *pdev, void *priv)

{

	struct imx_priv_data *dwmac = priv;



	if (dwmac->clk_tx)

		clk_disable_unprepare(dwmac->clk_tx);

	clk_disable_unprepare(dwmac->clk_mem);

}



static void imx_dwmac_fix_speed(void *priv, unsigned int speed)

{

	struct plat_stmmacenet_data *plat_dat;

	struct imx_priv_data *dwmac = priv;

	unsigned long rate;

	int err;



	plat_dat = dwmac->plat_dat;



	if (dwmac->ops->mac_rgmii_txclk_auto_adj ||

	    (plat_dat->interface == PHY_INTERFACE_MODE_RMII) ||

	    (plat_dat->interface == PHY_INTERFACE_MODE_MII))

		return;



	switch (speed) {

	case SPEED_1000:

		rate = 125000000;

		break;

	case SPEED_100:

		rate = 25000000;

		break;

	case SPEED_10:

		rate = 2500000;

		break;

	default:

		dev_err(dwmac->dev, "invalid speed %u\n", speed);

		return;

	}



	err = clk_set_rate(dwmac->clk_tx, rate);

	if (err < 0)

		dev_err(dwmac->dev, "failed to set tx rate %lu\n", rate);

}



static int

imx_dwmac_parse_dt(struct imx_priv_data *dwmac, struct device *dev)

{

	struct device_node *np = dev->of_node;

	int err = 0;



	if (of_get_property(np, "snps,rmii_refclk_ext", NULL))

		dwmac->rmii_refclk_ext = true;



	dwmac->clk_tx = devm_clk_get(dev, "tx");

	if (IS_ERR(dwmac->clk_tx)) {

		dev_err(dev, "failed to get tx clock\n");

		return PTR_ERR(dwmac->clk_tx);

	}



	dwmac->clk_mem = NULL;

	if (of_machine_is_compatible("fsl,imx8dxl")) {

		dwmac->clk_mem = devm_clk_get(dev, "mem");

		if (IS_ERR(dwmac->clk_mem)) {

			dev_err(dev, "failed to get mem clock\n");

			return PTR_ERR(dwmac->clk_mem);

		}

	}



	if (of_machine_is_compatible("fsl,imx8mp")) {

		/* Binding doc describes the propety:

		   is required by i.MX8MP.

		   is optinoal for i.MX8DXL.

		 */

		dwmac->intf_regmap = syscon_regmap_lookup_by_phandle(np, "intf_mode");

		if (IS_ERR(dwmac->intf_regmap))

			return PTR_ERR(dwmac->intf_regmap);



		err = of_property_read_u32_index(np, "intf_mode", 1, &dwmac->intf_reg_off);

		if (err) {

			dev_err(dev, "Can't get intf mode reg offset (%d)\n", err);

			return err;

		}

	}



	return err;

}



static int imx_dwmac_probe(struct platform_device *pdev)

{

	struct plat_stmmacenet_data *plat_dat;

	struct stmmac_resources stmmac_res;

	struct imx_priv_data *dwmac;

	const struct imx_dwmac_ops *data;

	int ret;



	ret = stmmac_get_platform_resources(pdev, &stmmac_res);

	if (ret)

		return ret;



	dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL);

	if (!dwmac)

		return PTR_ERR(dwmac);



	plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);

	if (IS_ERR(plat_dat))

		return PTR_ERR(plat_dat);



	data = of_device_get_match_data(&pdev->dev);

	if (!data) {

		dev_err(&pdev->dev, "failed to get match data\n");

		ret = -EINVAL;

		goto err_match_data;

	}



	dwmac->ops = data;

	dwmac->dev = &pdev->dev;



	ret = imx_dwmac_parse_dt(dwmac, &pdev->dev);

	if (ret) {

		dev_err(&pdev->dev, "failed to parse OF data\n");

		goto err_parse_dt;

	}



	ret = dma_set_mask_and_coherent(&pdev->dev,

					DMA_BIT_MASK(dwmac->ops->addr_width));

	if (ret) {

		dev_err(&pdev->dev, "DMA mask set failed\n");

		goto err_dma_mask;

	}



	plat_dat->init = imx_dwmac_init;

	plat_dat->exit = imx_dwmac_exit;

	plat_dat->fix_mac_speed = imx_dwmac_fix_speed;

	plat_dat->bsp_priv = dwmac;

	dwmac->plat_dat = plat_dat;



	ret = imx_dwmac_init(pdev, dwmac);

	if (ret)

		goto err_dwmac_init;



	ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);

	if (ret)

		goto err_drv_probe;



	return 0;



err_dwmac_init:

err_drv_probe:

	imx_dwmac_exit(pdev, plat_dat->bsp_priv);

err_dma_mask:

err_parse_dt:

err_match_data:

	stmmac_remove_config_dt(pdev, plat_dat);

	return ret;

}



static struct imx_dwmac_ops imx8mp_dwmac_data = {

	.addr_width = 34,

	.mac_rgmii_txclk_auto_adj = false,

	.set_intf_mode = imx8mp_set_intf_mode,

};



static struct imx_dwmac_ops imx8dxl_dwmac_data = {

	.addr_width = 32,

	.mac_rgmii_txclk_auto_adj = true,

	.set_intf_mode = imx8dxl_set_intf_mode,

};



static const struct of_device_id imx_dwmac_match[] = {

	{ .compatible = "nxp,imx8mp-dwmac-eqos", .data = &imx8mp_dwmac_data },

	{ .compatible = "nxp,imx8dxl-dwmac-eqos", .data = &imx8dxl_dwmac_data },

	{ }

};

MODULE_DEVICE_TABLE(of, imx_dwmac_match);



static struct platform_driver imx_dwmac_driver = {

	.probe  = imx_dwmac_probe,

	.remove = stmmac_pltfr_remove,

	.driver = {

		.name           = "imx-dwmac",

		.pm		= &stmmac_pltfr_pm_ops,

		.of_match_table = imx_dwmac_match,

	},

};

module_platform_driver(imx_dwmac_driver);



MODULE_AUTHOR("NXP");

MODULE_DESCRIPTION("NXP imx8 DWMAC Specific Glue layer");

MODULE_LICENSE("GPL v2");

drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c

+2 −1
Original line number Diff line number Diff line
@@ -507,7 +507,8 @@ stmmac_probe_config_dt(struct platform_device *pdev, const char **mac) 


	if (of_device_is_compatible(np, "snps,dwmac-4.00") ||

	    of_device_is_compatible(np, "snps,dwmac-4.10a") ||

	    of_device_is_compatible(np, "snps,dwmac-4.20a")) {

	    of_device_is_compatible(np, "snps,dwmac-4.20a") ||

	    of_device_is_compatible(np, "snps,dwmac-5.10a")) {

		plat->has_gmac4 = 1;

		plat->has_gmac = 0;

		plat->pmt = 1;

CRA Git | Maintained and supported by SUSTech CRA and CCSE