Merge existing fixes from spi/for-5.8 (064e8af7) · Commits · 戴 / test

Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml

+17 −9

Original line number	Diff line number	Diff line
		@@ -34,12 +34,15 @@ properties:
		maxItems: 1

		clocks:
		maxItems: 1
		minItems: 1
		maxItems: 2
		items:
		- description: controller register bus clock
		- description: baud rate generator and delay control clock

		clock-names:
		description: input clock for the baud rate generator
		items:
		- const: core
		minItems: 1
		maxItems: 2

		if:
		properties:
		@@ -51,17 +54,22 @@ if:
		then:
		properties:
		clocks:
		contains:
		items:
		- description: controller register bus clock
		- description: baud rate generator and delay control clock
		minItems: 2

		clock-names:
		minItems: 2
		items:
		- const: core
		- const: pclk

		else:
		properties:
		clocks:
		maxItems: 1

		clock-names:
		items:
		- const: core

		required:
		- compatible
		- reg

drivers/spi/spi-fsl-dspi.c

+4 −4

Original line number	Diff line number	Diff line
		@@ -588,14 +588,14 @@ static void dspi_release_dma(struct fsl_dspi *dspi)
		return;

		if (dma->chan_tx) {
		dma_unmap_single(dma->chan_tx->device->dev, dma->tx_dma_phys,
		dma_bufsize, DMA_TO_DEVICE);
		dma_free_coherent(dma->chan_tx->device->dev, dma_bufsize,
		dma->tx_dma_buf, dma->tx_dma_phys);
		dma_release_channel(dma->chan_tx);
		}

		if (dma->chan_rx) {
		dma_unmap_single(dma->chan_rx->device->dev, dma->rx_dma_phys,
		dma_bufsize, DMA_FROM_DEVICE);
		dma_free_coherent(dma->chan_rx->device->dev, dma_bufsize,
		dma->rx_dma_buf, dma->rx_dma_phys);
		dma_release_channel(dma->chan_rx);
		}
		}

drivers/spi/spi-rspi.c

+21 −7

Original line number	Diff line number	Diff line
		@@ -179,7 +179,7 @@

		struct rspi_data {
		void __iomem *addr;
		u32 max_speed_hz;
		u32 speed_hz;
		struct spi_controller *ctlr;
		struct platform_device *pdev;
		wait_queue_head_t wait;
		@@ -258,8 +258,7 @@ static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
		rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);

		/* Sets transfer bit rate */
		spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk),
		2 * rspi->max_speed_hz) - 1;
		spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 2 * rspi->speed_hz) - 1;
		rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);

		/* Disable dummy transmission, set 16-bit word access, 1 frame */
		@@ -299,14 +298,14 @@ static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size)

		clksrc = clk_get_rate(rspi->clk);
		while (div < 3) {
		if (rspi->max_speed_hz >= clksrc/4) /* 4=(CLK/2)/2 */
		if (rspi->speed_hz >= clksrc/4) /* 4=(CLK/2)/2 */
		break;
		div++;
		clksrc /= 2;
		}

		/* Sets transfer bit rate */
		spbr = DIV_ROUND_UP(clksrc, 2 * rspi->max_speed_hz) - 1;
		spbr = DIV_ROUND_UP(clksrc, 2 * rspi->speed_hz) - 1;
		rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
		rspi->spcmd \|= div << 2;

		@@ -341,7 +340,7 @@ static int qspi_set_config_register(struct rspi_data *rspi, int access_size)
		rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);

		/* Sets transfer bit rate */
		spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 2 * rspi->max_speed_hz);
		spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 2 * rspi->speed_hz);
		rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);

		/* Disable dummy transmission, set byte access */
		@@ -949,9 +948,24 @@ static int rspi_prepare_message(struct spi_controller *ctlr,
		{
		struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
		struct spi_device *spi = msg->spi;
		const struct spi_transfer *xfer;
		int ret;

		rspi->max_speed_hz = spi->max_speed_hz;
		/*
		* As the Bit Rate Register must not be changed while the device is
		* active, all transfers in a message must use the same bit rate.
		* In theory, the sequencer could be enabled, and each Command Register
		* could divide the base bit rate by a different value.
		* However, most RSPI variants do not have Transfer Data Length
		* Multiplier Setting Registers, so each sequence step would be limited
		* to a single word, making this feature unsuitable for large
		* transfers, which would gain most from it.
		*/
		rspi->speed_hz = spi->max_speed_hz;
		list_for_each_entry(xfer, &msg->transfers, transfer_list) {
		if (xfer->speed_hz < rspi->speed_hz)
		rspi->speed_hz = xfer->speed_hz;
		}

		rspi->spcmd = SPCMD_SSLKP;
		if (spi->mode & SPI_CPOL)

drivers/spi/spi-sprd-adi.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -389,9 +389,9 @@ static int sprd_adi_restart_handler(struct notifier_block *this,
		sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_CTRL, val);

		/* Load the watchdog timeout value, 50ms is always enough. */
		sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOAD_HIGH, 0);
		sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOAD_LOW,
		WDG_LOAD_VAL & WDG_LOAD_MASK);
		sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOAD_HIGH, 0);

		/* Start the watchdog to reset system */
		sprd_adi_read(sadi, sadi->slave_pbase + REG_WDG_CTRL, &val);

include/uapi/linux/spi/spidev.h

+4 −0

Original line number	Diff line number	Diff line
		@@ -48,6 +48,10 @@
		#define SPI_TX_QUAD 0x200
		#define SPI_RX_DUAL 0x400
		#define SPI_RX_QUAD 0x800
		#define SPI_CS_WORD 0x1000
		#define SPI_TX_OCTAL 0x2000
		#define SPI_RX_OCTAL 0x4000
		#define SPI_3WIRE_HIZ 0x8000

		/---------------------------------------------------------------------------/

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